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CAT28C513 Dataheets PDF



Part Number CAT28C513
Manufacturers Catalyst Semiconductor
Logo Catalyst Semiconductor
Description 512K-Bit CMOS PARALLEL E2PROM
Datasheet CAT28C513 DatasheetCAT28C513 Datasheet (PDF)

Advanced CAT28C512/513 512K-Bit CMOS PARALLEL E2PROM FEATURES s Fast Read Access Times: 120/150 ns s Low Power CMOS Dissipation: s Automatic Page Write Operation: –Active: 50 mA Max. –Standby: 200 µA Max. s Simple Write Operation: –1 to 128 Bytes in 5ms –Page Load Timer s End of Write Detection: –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: –Toggle Bit –DATA Polling s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s.

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Advanced CAT28C512/513 512K-Bit CMOS PARALLEL E2PROM FEATURES s Fast Read Access Times: 120/150 ns s Low Power CMOS Dissipation: s Automatic Page Write Operation: –Active: 50 mA Max. –Standby: 200 µA Max. s Simple Write Operation: –1 to 128 Bytes in 5ms –Page Load Timer s End of Write Detection: –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: –Toggle Bit –DATA Polling s Hardware and Software Write Protection s 100,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and Automotive –5ms Max s CMOS and TTL Compatible I/O Temperature Ranges DESCRIPTION The CAT28C512/513 is a fast,low power, 5V-only CMOS parallel E2PROM organized as 64K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C512/513 features hardware and software write protection. The CAT28C512/513 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 32-pin DIP, PLCC, 32-pin TSOP and 40-pin TSOP packages. BLOCK DIAGRAM A7–A15 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 65,536 x 8 E2PROM ARRAY 128 BYTE PAGE REGISTER VCC HIGH VOLTAGE GENERATOR CE OE WE CONTROL I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER 5096 FHD F02 I/O0–I/O7 A0–A6 ADDR. BUFFER & LATCHES © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25074-00 2/98 CAT28C512/513 Advanced PIN CONFIGURATION DIP Package (P) PLCC Package (N) A12 A15 NC NC VCC WE NC PLCC Package (N) A14 A15 VCC WE A7 A12 A13 29 28 27 CAT28C513 TOP VIEW 26 25 24 23 NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 1 32 31 30 5 29 6 28 7 27 8 26 CAT28C512 9 25 TOP VIEW 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A14 A13 A8 A9 A11 OE A10 CE I/O7 4 3 2 1 32 31 30 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 A8 A9 A11 NC OE A10 CE I/O7 I/O6 12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 5096 FHD F01 TSOP Package (10mm X 14mm) (T14) A11 A9 A8 A13 A14 NC NC NC WE VCC NC NC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A0 A1 A2 A3 TSOP Package (8mmx20mm) (T) I/O5 CAT28C512 TOP VIEW A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CAT28C512 TOP VIEW 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 I/O0 A0 A1 A2 A3 PIN FUNCTIONS Pin Name A0–A15 I/O0–I/O7 CE OE Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable Pin Name WE VCC VSS NC Function Write Enable 5V Supply Ground No Connect Doc. No. 25074-00 2/98 2 Advanced CAT28C512/513 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(2) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(3) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(4) Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 104 or 105 100 2000 100 Max. *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Units Cycles/Byte Years Volts mA Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = 5V ±10%, unless otherwise specified. Limits Symbol ICC ICCC(5) ISB ISBC(6) ILI ILO VIH(6) VIL(5) VOH VOL VWI Parameter VCC Current (Operating, TTL) VCC Current (Operating, CMOS) VCC Current (Standby, TTL) VCC Current (Standby, CMOS) Input Leakage Current Output Leakage Current High Level Input Voltage Low Level Input .


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