Power MOSFET. SSM9977GM Datasheet

SSM9977GM MOSFET. Datasheet pdf. Equivalent

SSM9977GM Datasheet
Recommendation SSM9977GM Datasheet
Part SSM9977GM
Description Dual N-channel Enhancement-mode Power MOSFET
Feature SSM9977GM; SSM9977M/GM DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement Lower gate charg.
Manufacture Silicon Standard
Datasheet
Download SSM9977GM Datasheet




Silicon Standard SSM9977GM
SSM9977M/GM
DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Simple drive requirement
Lower gate charge
Fast switching characteristics
Description
D2
D2
D1
D1
SO-8
G2
S2
G1
S1
BV DSS
R DS(ON)
ID
60V
90m
3.5A
D1 D2
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
The SSM9977M is in the SO-8 package, which is widely preferred for
commercial and industrial surface mount applications, and is well suited
for low voltage applications such as DC/DC converters.
G1
G2
S1
S2
This device is available with Pb-free lead finish (second-level interconnect) as SSM9977GM.
Absolute Maximum Ratings
Symbol
Parameter
VDS
VGS
ID @ TA=25°C
ID @ TA=100°C
IDM
PD @ TA=25°C
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
Total Power Dissipation
Linear Derating Factor
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
Rating
60
± 25
3.5
2.8
20
2
0.016
-55 to 150
-55 to 150
Units
V
V
A
A
A
W
W/°C
°C
°C
Thermal Data
Symbol
Rthj-a
Parameter
Thermal Resistance Junction-ambient3
Max.
Value
62.5
Unit
°C/W
8/21/2004 Rev.2.01
www.SiliconStandard.com
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Silicon Standard SSM9977GM
SSM9977M/GM
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
BVDSS
∆ ∆BVDSS/ Tj
RDS(ON)
VGS(th)
gfs
IDSS
IGSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Rg
Drain-Source Breakdown Voltage
VGS=0V, ID=250uA
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
Static Drain-Source On-Resistance2 VGS=10V, ID=3A
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current (Tj=25oC)
Drain-Source Leakage Current (Tj=70oC)
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
Turn-off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=4.5V, ID=2A
VDS=VGS, ID=250uA
VDS=10V, ID=3A
VDS=60V, VGS=0V
VDS=48V, VGS=0V
VGS=±25V
ID=3A
VDS=48V
VGS=4.5V
VDS=30V
ID=1A
RG=3.3, VGS=10V
RD=30
VGS=0V
VDS=25V
f=1.0MHz
Gate Resistance
f=1.0MHz
60 - - V
- 0.04 - V/°C
- - 90 m
- - 120 m
1 - 3V
-6-S
- - 10 uA
- - 25 uA
- - ±100 nA
- 6 10 nC
- 2 - nC
- 3 - nC
- 6 - ns
- 5 - ns
- 16 - ns
- 3 - ns
- 510 810 pF
- 55 - pF
- 35 - pF
- 1.3 -
Source-Drain Diode
Symbol
VSD
trr
Parameter
Forward On Voltage2
Reverse Recovery Time2
Qrr Reverse Recovery Charge
Test Conditions
IS=1.7A, VGS=0V
IS=4A, VGS=0V,
dI/dt=100A/µs
Min. Typ. Max. Units
- - 1.2 V
- 27 - ns
- 32 - nC
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board, t <10sec ; 135°C/W when mounted on min. copper pad.
8/21/2004 Rev.2.01
www.SiliconStandard.com
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Silicon Standard SSM9977GM
25
T A = 25 o C
20
15
10V
7.0 V
5.0V
4.5V
10
V G =3.0V
5
0
02468
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
25
T A = 150 o C
20
15
SSM9977M/GM
10V
7.0V
5.0V
4.5V
10
V G =3.0V
5
0
0246
V DS , Drain-to-Source Voltage (V)
8
Fig 2. Typical Output Characteristics
100
ID=2A
T A =25°C
90
80
70
2 4 6 8 10
V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
4
2.0
1.8 I D = 3 A
V G =10V
1.6
1.4
1.2
1.0
0.8
0.6
-50 0 50 100
T j , Junction Temperature ( o C)
150
Fig 4. Normalized On-Resistance
vs. Junction Temperature
1.8
3
2
T j =150 o C
1
T j =25 o C
1.5
1.2
0.9
0.6
0
0 0.2 0.4 0.6 0.8 1
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
1.2
0.3
-50 0 50 100
T j , Junction Temperature ( o C)
150
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
8/21/2004 Rev.2.01
www.SiliconStandard.com
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