M5M4V4405CJ-7

MITSMUIBTSISUHBI ISLHSIsLSIs M5M4V4405MC5JM,4TVP44-065,C-J7,T,-P6-6S,-7,,--76SS,-7S EDOE(DHOYP(HEYRPPEARGPEAMGOEDMEO) D41E9)44310944-3B0I4T-B(1I0T4(180547865-W76O-WRDORBDY B4-YB4IT-B) DITY)NDAYMNIACMRICAMRAM DESCRIPTION This is a family of 1048576-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. PIN CONFIGURATION (TOP VIEW) DQ1 1 DQ2 2 W3 RAS 4 A9 5 26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE FEATURES Type name RAS CAS Address OE access access access access time time time time Cycle...