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CAT93C66 Dataheets PDF



Part Number CAT93C66
Manufacturers Catalyst Semiconductor
Logo Catalyst Semiconductor
Description 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
Datasheet CAT93C66 DatasheetCAT93C66 Datasheet (PDF)

CAT93C46/56/57/66/86 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM FEATURES s High Speed Operation: s Power-Up Inadvertant Write Protection s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and Automotive – 93C46/56/57/66: 1MHz – 93C86: 3MHz s Low Power CMOS Technology s 1.8 to 6.0 Volt Operation s Selectable x8 or x16 Memory Organization s Self-Timed Write Cycle with Auto-Clear s Hardware and Software Write Protection Temperature Ranges s Sequential Read (excep.

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CAT93C46/56/57/66/86 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM FEATURES s High Speed Operation: s Power-Up Inadvertant Write Protection s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial and Automotive – 93C46/56/57/66: 1MHz – 93C86: 3MHz s Low Power CMOS Technology s 1.8 to 6.0 Volt Operation s Selectable x8 or x16 Memory Organization s Self-Timed Write Cycle with Auto-Clear s Hardware and Software Write Protection Temperature Ranges s Sequential Read (except 93C46) s Program Enable (PE) Pin (93C86 only) DESCRIPTION The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial E2PROM memory devices which are configured as either registers of 16 bits (ORG pin at VCC) or 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C46/56/ 57/66/86 are manufactured using Catalyst’s advanced CMOS E2PROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages. PIN CONFIGURATION DIP Package (P) CS SK DI DO 1 2 3 4 8 7 6 5 SOIC Package (J) 1 2 3 4 8 7 6 5 ORG GND DO DI SOIC Package (S) CS SK DI DO 1 2 3 4 8 7 6 5 SOIC Package (K) 1 2 3 4 8 7 6 5 VCC NC (PE*) ORG GND TSSOP Package (U) CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC (PE*) ORG GND VCC NC (PE*) NC (PE*) VCC ORG CS GND SK VCC CS NC (PE*) SK ORG DI GND DO *Only For 93C86 PIN FUNCTIONS Pin Name CS SK DI DO VCC GND ORG NC PE* Function Chip Select Clock Input Serial Data Input Serial Data Output +1.8 to 6.0V Power Supply Ground Memory Organization No Connection Program Enable 93C46/56/57/66/86 F01 BLOCK DIAGRAM VCC GND ORG MEMORY ARRAY ORGANIZATION ADDRESS DECODER DATA REGISTER DI CS PE* MODE DECODE LOGIC OUTPUT BUFFER Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization. SK CLOCK GENERATOR DO 93C46/56/57/66/86 F02 © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 25056-00 2/98 M-1 93C46/56/57/66/86 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. –55°C to +125°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to Ground(1) ............ –2.0V to +VCC +2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100 mA RELIABILITY CHARACTERISTICS Symbol NEND TDR (3) (3) *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Parameter Endurance Data Retention ESD Susceptibility Latch-Up Min. 1,000,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 VZAP(3) ILTH(3)(4) D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB1 ISB2(5) ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Operating Write) Power Supply Current (Operating Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC-0.2 2.4 0.2 -0.1 2 0 VCCX0.7 Min. Typ. Max. 3 500 10 0 1 1 0.8 VCC+1 VCCX0.2 VCC+1 0.4 Units mA µA µA µA µA µA Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG=GND CS=0V ORG=Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5V≤VCC<5.5V 1.8V≤VCC<2.7V 4.5V≤VCC<5.5V IOL = 2.1mA IOH = -400µA 1.8V≤VCC<2.7V V V V V V V V IOL = 1mA IOH = -100µA Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Standby Current (ISB2).


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