P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
‐20V
D
RDSON (MAX.)
...
P‐Channel Logic Level Enhancement Mode Field Effect
Transistor
Product Summary:
BVDSS
‐20V
D
RDSON (MAX.)
44mΩ
ID ‐4A G
S
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
Gate‐Source Voltage
VGS ±12
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 70 °C
ID IDM
‐4 ‐3 ‐16
Power Dissipation
TA = 25 °C TA = 70 °C
Operating Junction & Storage Temperature Range
PD Tj, Tstg
1.25 0.8 ‐55 to 150
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
TYPICAL
MAXIMUM
Junction‐to‐Ambient3
RJA
Junction‐to‐Lead4
RJL
1Pulse width limited by maximum junction temperature. 2Duty cycle 1% 3100°C / W when mounted on a 1 in2 pad of 2 oz...