Dual P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
‐100V
RDSON (MA...
Dual P‐Channel Logic Level Enhancement Mode Field Effect
Transistor
Product Summary:
BVDSS
‐100V
RDSON (MAX.)
250mΩ
ID ‐2.5A
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source Voltage
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
VGS ID IDM PD Tj, Tstg
TYPICAL
Junction‐to‐Case
RJC
Junction‐to‐Ambient
RJA
1Pulse width limited by maximum junction temperature. 2Duty cycle 1%
2012/9/21
EMBB5B10G
LIMITS ±20 ‐2.5 ‐1.8 ‐10 2 0.8
‐55 to 150
UNIT V
A
W °C
...