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CCU3001 Dataheets PDF



Part Number CCU3001
Manufacturers ETC
Logo ETC
Description Central Control Unit
Datasheet CCU3001 DatasheetCCU3001 Datasheet (PDF)

MICRONAS INTERMETALL CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I, Central Control Unit MICRONAS Edition Feb. 14, 1995 6251-367-1DS CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I Contents Page 4 4 5 5 5 5 5 5 5 5 6 7 7 7 8 8 10 12 14 19 21 21 22 22 22 22 23 23 24 25 28 31 32 32 32 32 33 34 34 36 36 37 38 59 61 62 2 Section 1. 1.1. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.9. 2.10. 2.11. 2.12. 2.13. 2.14. 2.15. 2.16. 3. 3.1. 3.2. 3.3. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4..

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MICRONAS INTERMETALL CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I, Central Control Unit MICRONAS Edition Feb. 14, 1995 6251-367-1DS CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I Contents Page 4 4 5 5 5 5 5 5 5 5 6 7 7 7 8 8 10 12 14 19 21 21 22 22 22 22 23 23 24 25 28 31 32 32 32 32 33 34 34 36 36 37 38 59 61 62 2 Section 1. 1.1. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.9. 2.10. 2.11. 2.12. 2.13. 2.14. 2.15. 2.16. 3. 3.1. 3.2. 3.3. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.5. 4.6.6. 4.6.7. 4.6.8. 4.6.9. 4.6.10. 5. 6. 7. Title Introduction Features of the CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I Functional Description ROM RAM CPU Clock Generator PORT 1 to PORT 3, PORT 6 to PORT 8 PORT 4 I/O-Lines P50 to P55 Special Mode of Port 7 Power-down Control External Memory (Special Mode P77) R/W Output (Special Mode P76) Banking Address (Special Mode P70 to P75) Reset Function Control Register Interrupt Controller IM Bus Interface Multifunctional Timer Watchdog IR-Input Mask Options Definitions Interrupt Definitions Memory Mappings I/O Definitions Specifications Outline Dimensions Pin Configuration Pin Connections and Short Descriptions Pin Descriptions Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics DC Characteristics Using External Devices AC Characteristics IM Bus Waveforms Description of the IM Bus Recommended Operating Conditions of IM Bus Registers Index Addendum: CCU 3000, CCU 3000-I EMU Versions Addendum: CCU 3000 1 µm Version MICRONAS INTERMETALL CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I Contents, continued Page 62 62 63 63 64 65 66 66 66 66 66 66 67 71 73 74 76 Section 7.1. 7.1.1. 7.1.2. 7.1.3. 7.1.4. 7.1.5. 8. 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.7.1. 8.8. 9. Title Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics DC Characteristics AC Characteristics Addendum: CCU 3000-I Specification Changes to CCU3000 Definitions Interrupt Definitions Memory Mappings I/O Definitions I2C and IM Bus Interface Pin Connections and Short Descriptions DC Parameters I2C Bus Master Interface List of Registers that Differ from CCU 3000, CCU 3001 Data Sheet History MICRONAS INTERMETALL 3 CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I 1. Introduction The CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I are integrated circuits designed in 1.2 µm CMOS technology, with the exception of CCU 3000, TC18 and TC19, which is designed in 1 µm CMOS technology. The CPU contained on the chips is a functionally unchanged 65C02-core, which means that for program development, systems can be used which are on the market; including high level language compilers. The pin numbers mentioned in this data sheet refer to the 68-pin PLCC package unless otherwise designated. The CCU 3000-I is described separately in an addendum on page 66. – 51 I/O lines (CCU 3001) – 26 I/O lines (CCU 3000) – clock generator with programmable clock frequency – 8 level interrupt controller – CCU 3000, CCU 3001: 2 Multimaster IM bus interfaces – CCU 3000-I, CCU 3001-I: 1I2C/IM bus and 1 Multimaster IM bus interface (see addendum) – IR-input for software-decoded IR-systems – on-chip power on, stand-by and clock supervision logic – on-chip watchdog – 3 multifunctional timers 1.1. Features of the CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I – CCU 3000 = ROM-less version of the CCU 3001 – 65C02 CPU with max. 8 MHz clock – 32 kByte internal ROM (CCU 3001 only) – 1344 internal Bytes RAM with stand-by option – supports memory banking (external 2MBytes) – power down signal for external memory – mask option: EMU mode – programs can be written in Assembler or in “C” – CCU 3000 TC 18/19: 1.0 µm CMOS technology, (see addendum) – application software available A0 to A15 (P20 to P37) 16 1 R/W/P40 D0 to D7 (P10 to P17) 8 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 6 8 8 5 P5 P6 P7 P8 Watch– dog 3 CPU IM 1 Power on Logic INTERRUPT CONTROLLER IM 2 3 Stand– by Logic ROM 32 kByte (3001 only) RAM 1344 Bytes 1 IR TIMER1 TIMER2 TIMER3 CLOCK 1 1 1 2 MICRONAS INTERMETALL Fig. 1–1: CCU 3000, CCU 3001 block diagram 4 CCU 3000, CCU 3000-I CCU 3001, CCU 3001-I 2. Functional Description 2.1. ROM The chip is equipped with 32 kByte mask-programmable ROM. The ROM uses up the address space from 8000H to FFFFH. This ROM can be supplemented or replaced externally. Only the CCU 3001 has an internal ROM. 2.2. RAM The RAM area is split into three parts: – page 0 – page 1 – page 3, 4, 5, 6 (address 0 to FF.


CCU3000-I CCU3001 BZX84-B10


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