MBM29DL400TC-55

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20866-2E FLASH MEMORY CMOS 4M (512K × 8/256K × 16) BIT MBM29DL400TC-55/-70/-90/-12/MBM29DL400BC-55/-70/-90/-12 s FEATURES Single 3.0 V read, program, and erase Minimizes system level power requirements Simultaneous operations Read-while-Erase or Read-while-Program Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts (Pin compatible with MBM29LV400TC/BC) 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) Minimum 100,000 program/erase cycles High performance 55 ns maximum access time Sector erase architecture Two 16K byte, four 8K bytes, two 32K byte, and six 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. Boot Code Sector Architecture T = Top sector B = Bottom sector Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any se...