MBM29F200BC-70

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20867-3E FLASH MEMORY CMOS www.datasheet4u.com 2M (256K × 8/128K × 16) BIT MBM29F200TC-55/-70/-90/MBM29F200BC-55/-70/-90 s FEATURES Single 5.0 V read, write, and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF) Minimum 100,000 write/erase cycles High performance 55 ns maximum access time Sector erase architecture One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes. Any combination of sectors can be concurrently erased. Also supports full chip erase. Boot Code Sector Architecture T = Top sector B = Bottom sector Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector Embedded ProgramTM Algorithms Automatically writes and verif...