MBM29LV160T-80

FUJITSU SEMICONDUCTOR DATA SHEET DS05-20846-4E FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 s FEATURES Single 3.0 V read, program and erase Minimizes system level power requirements Compatible with JEDEC-standard commands Uses same software commands as E2PROMs Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 46-pin SON (Package suffix: PN) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT) Minimum 100,000 program/erase cycles High performance 80 ns maximum access time Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase Boot Code Sector Architecture T = Top sector B = Bottom sector ...