Document
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-20865-3E
FLASH MEMORY
CMOS
2M (256K × 8/128K × 16) BIT
MBM29LV200TC-70/-90/-12/MBM29LV200BC-70/-90/-12
s FEATURES
• Single 3.0 V read, program, and erase Minimizes system level power requirements
• Compatible with JEDEC-standard commands Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type) 44-pin SOP (Package suffix: PF)
• Minimum 100,000 program/erase cycles • High performance
70 ns maximum access time • Sector erase architecture
One 8K word, two 4K words, one 16K word, and three 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM Algorithms Automatically pre-programs and era.