Msps ADC. AT84AD004B Datasheet

AT84AD004B Datasheet PDF, Equivalent


Part Number

AT84AD004B

Description

Dual 8-bit 500 Msps ADC

Manufacture

e2v

Total Page 30 Pages
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AT84AD004B Datasheet
Datasheet
AT84AD004B
Dual 8-bit 500 Msps ADC
1. Features
Dual ADC with 8-bit Resolution
500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode
Single or 1:2 Demultiplexed Output
LVDS Output Format (100Ω)
500 mVpp Analog Input (Differential Only)
Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
LQFP144 or LQFP-ep 144L Green packages
Temperature Range:
– 0°C < Tamb < 70° C (Commercial Grade)
– –40°C < Tamb < 85° C (Industrial Grade)
3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– interleaving Functions:
• Offset and Gain (Channel to Channel) Calibration
• Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
2. Performance
Low Power Consumption: 0.7W per Channel
Power Consumption in Standby Mode: 120 mW
1 GHz Full Power Input Bandwidth (–3 dB)
SNR = 45 dB Typ (7.2 ENOB), THD = –53 dBc, SFDR = –56 dBc at Fs = 500 Msps
Fin = 250 MHz
2-tone IMD3: –54 dBc (249 MHz, 251 MHz) at 500 Msps
DNL = 0.25 LSB, INL = 0.5 LSB
Low Bit Error Rate (10–18) at 500 Msps
e2v semiconductors SAS 2009
Visit our website: www.e2v.com
for the latest version of the datasheet
0818F–BDC–09/09

AT84AD004B Datasheet
AT84AD004B
3. Application
• Digital Oscilloscopes
• Communication Receivers (I/Q)
• Direct RF Down Conversion
• High Speed Data Acquisition
• Radar/ECM
4. Description
The AT84AD004B is a monolithic dual 8-bit analog-to-digital converter, offering low 1.4W power con-
sumption and excellent digitizing accuracy. It integrates dual on-chip track/holds that provide an
enhanced dynamic performance with a sampling rate of up to 500 Msps and an input frequency band-
width of 1 GHz. The dual concept, the integrated demultiplexer and the easy interleaving mode make
this device user-friendly for all dual channel applications, such as direct RF conversion or data acquisi-
tion. The smart function of the 3-wire serial interface eliminates the need for external components, which
are usually necessary for gain and offset tuning and setting of other parameters, leading to space and
power reduction as well as system flexibility.
5. Functional Description
The AT84AD004B is a dual 8-bit 500 Msps ADC based on advanced high-speed
BiCMOS technology.
Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H), and an 8-bit
flash-like architecture core analog-to-digital converter. The output data is followed by a switchable 1:1 or
1:2 demultiplexer and LVDS output buffers (100Ω).
Two over-range bits are provided for adjustment of the external gain control on each channel.
A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several adjustments:
• Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus interface (steps of
0.011 dB)
• Analog input switch: both ADCs can convert the same analog input signal I or Q
• Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the output frequency
on the data ready output signal
• Partial or full standby on channel I or channel Q
• Clock selection:
– Two independent clocks: CLKI and CLKQ
– One master clock (CLKI) with the same phase for channel I and channel Q
– One master clock but with two phases (CLKI for channel I and CLKIB for channel Q)
• ISA: Internal Settling Adjustment on channel I and channel Q
• FiSDA: Fine Sampling Delay Adjustment on channel Q
• Adjustable Data Ready Output Delay on both channels
• Test mode: decimation mode (by 16), Built-in Test
2
0818F–BDC–09/09
e2v semiconductors SAS 2009


Features Datasheet pdf Datasheet AT84AD004B Dual 8-bit 500 Msp s ADC 1. Features • Dual ADC with 8- bit Resolution • 500 Msps Sampling Ra te per Channel, 1 Gsps in interleaved M ode • Single or 1:2 Demultiplexed Out put • LVDS Output Format (100Ω) • 500 mVpp Analog Input (Differential Onl y) • Differential or Single-ended 50 PECL/LVDS Compatible Clock Inputs • Power Supply: 3.3V (Analog), 3.3V (Dig ital), 2.25V (Output) • LQFP144 or LQ FP-ep 144L Green packages • Temperatu re Range: – 0°C < Tamb < 70° C (Com mercial Grade) – –40°C < Tamb < 85 ° C (Industrial Grade) • 3-wire Seri al Interface – 16-bit Data, 3-bit Add ress – 1:2 or 1:1 Output Demultiplexe r Ratio Selection – Full or Partial S tandby Mode – Analog Gain (±1.5 dB) Digital Control – Input Clock Selecti on – Analog Input Switch Selection Binary or Gray Logical Outputs – Sy nchronous Data Ready Reset – Data Rea dy Delay Adjustable on Both Channels interleaving Functions: • Offset and Gain (Channel to Chann.
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