function gate. 74AXP1T57 Datasheet

74AXP1T57 gate. Datasheet pdf. Equivalent

Part 74AXP1T57
Description Dual supply configurable multiple function gate
Feature 74AXP1T57 Dual supply configurable multiple function gate Rev. 5 — 3 July 2017 Product data sheet.
Manufacture nexperia
Datasheet
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74AXP1T57
74AXP1T57
Dual supply configurable multiple function gate
Rev. 5 — 3 July 2017
Product data sheet
1 General description
The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger
inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (VCCI and
VCCO). The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs
can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between
0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This
feature allows voltage level translation. The 74AXP1T57 can be configured as any of the
following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.
This device ensures very low static and dynamic power consumption across the entire
supply range and is fully specified for partial power down applications using IOFF. The
IOFF circuitry disables the output, preventing the potentially damaging backflow current
through the device when it is powered down.
2 Features and benefits
Wide supply voltage range:
VCCI: 0.7 V to 2.75 V
VCCO: 1.2 V to 5.5 V
Low input capacitance; CI = 0.6 pF (typical)
Low output capacitance; CO = 1.8 pF (typical)
Low dynamic power consumption; CPD = 0.6 pF at VCCI = 1.2 V (typical)
Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)
Low static power consumption; ICCI = 0.5 μA (85 °C maximum)
Low static power consumption; ICCO = 1.8 μA (85 °C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
JESD8-C (2.7 V to 3.6 V; Y output)
JESD12-6 (4.5 V to 5.5 V; Y output)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD78D Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10 % of VCCO
IOFF circuitry provides partial power-down mode operation
Multiple package options



74AXP1T57
Nexperia
74AXP1T57
Dual supply configurable multiple function gate
Specified from -40 °C to +85 °C
3 Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
74AXP1T57DC -40 °C to +85 °C
74AXP1T57GT -40 °C to +85 °C
74AXP1T57GN -40 °C to +85 °C
74AXP1T57GS -40 °C to +85 °C
74AXP1T57GX -40 °C to +85 °C
Name Description
Version
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
SOT1116
XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
SOT1203
X2SON8 plastic thermal enhanced extremely thin small outline
SOT1233
package; no leads; 8 terminals; body 1.35 x 0.8 x 0.35 mm
4 Marking
Table 2. Marking
Type number
74AXP1T57DC
74AXP1T57GT
74AXP1T57GN
74AXP1T57GS
74AXP1T57GX
Marking code [1]
rD
rD
rD
rD
rD
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5 Functional diagram
A2
B3
C7
Figure 1.  Logic symbol
6Y
aaa-018525
A2
B3
C7
VCCI
Figure 2.  Logic diagram
6Y
VCCO
aaa-018526
74AXP1T57
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 3 July 2017
© Nexperia B.V. 2017. All rights reserved.
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