LATCHED DRIVER. M54972P Datasheet

M54972P DRIVER. Datasheet pdf. Equivalent

Part M54972P
Description Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
Feature MITSUBISHI M54972P/FP Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER DESCRIPTION T.
Manufacture Mitsubishi
Datasheet
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MITSUBISHI M54972P/FP Bi-CMOS 8-BIT SE M54972P Datasheet
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M54972P
MITSUBISHI <CONTROL / DRIVER IC>
M54972P/FP
Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M54972 is a semiconductor integrated circuit consisting of 8
stages of CMOS shift registers and latches with serial inputs and
serial or parallel outputs. It is based on Bi-CMOS process
technology, and has 8 bipolar drivers at the parallel outputs.
FEATURES
q Serial input and serial or parallel output
q Serial output enables cascade connection
q Built-in latch for each stage
q Enable input provides output control
q Low supply current (standby current ICC 10µA)
q Serial I/O level is compatible with typical CMOS devices
q Driver features: High withstand voltage (BVCEO 30V)
Capable of large drive currents (IO(max)=300mA)
Low output saturation voltage VOL < 0.6V at lo=300mA
q Wide operating temperature range Ta=-20 – +75°C
PIN CONFIGURATION (TOP VIEW)
Clock
T1
Serial input S-IN 2
Logic GND L-GND 3
Power supply VCC 4
Serial output S-OUT 5
Latch input LATCH 6
Enable input
EN 7
Driver GND P-GND 8
16 O1
15 O2
14 O3
13 O4
12 O5
11 O6
10 O7
9 O8
Outline 16P4(P)
16P2N-A(FP)
Parallel outputs
APPLICATION
Dot drivers for thermal print heads. Serial/parallel conversion.
Drivers for relays and solenoids.
FUNCTION
The M54972 consists of 8 stages of D-type flip flops connected to
8 latches.
Data is input to serial input S-IN, and clock pulses are input to
clock input T. When the clock changes from low to high, the input
data enters the first shift register and data already in the shift
registers is shifted sequentially.
The serial output S-OUT is used to connect multiple M54972 to
expand the number of parallel outputs. S-OUT is connected to S-IN
of the next stage.
For parallel output. When the clock pulse changes from low to
high, latch input (LATCH) is high and output enable input (EN) is
low the serial input data at S-IN appears at output O1 and the other
data already present is shifted sequentially to outputs O2 through
O8.
The parallel outputs are inverted.
When the latch input is held low, the latch retains the stored data.
When the EN input is high, outputs O1 through O8 all turn off. As
the internal logic is unstable when the power is turned on, the EN
input should be kept high (setting outputs O1 through O8 off) until
input data is set and the internal logic is initialized.
L-GND is the GND of CMOS logic circuit and P-GND is the GND of
output driver circuits O1 through O8 which employ bipolar
transistors capable of large drive currents.
BLOCK DIAGRAM
Parallel outputs
O1 O2 O3 O4 O5 O6 O7 O8
16 15 14 13 12 11 10
9
Power supply
VCC 4
8 P-GND Driver GND
Enable input
EN 7
Latch input LATCH 6
Q QQQ QQQ Q
LD LD LD LD LD LD LD LD
Serial input S-IN 2
Clock
T1
DQ DQ DQ DQ DQ DQ DQ DQ
TTTTTTTT
3
L-GND
Logic GND
5 S-OUT Serial output



M54972P
MITSUBISHI <CONTROL / DRIVER IC>
M54972P/FP
Bi-CMOS 8-BIT SERIAL-INPUT LATCHED DRIVER
TIMING CHART
Serial input S-IN
Clock T
Latch input LATCH
Enable input EN
O1
O2
O3
Parallel outputs
O4
O5
O6
O7
O8
Serial output S-OUT
The shaded area shows the unstable state.
INPUT/OUTPUT CIRCUIT DIAGRAM
1 Inputs with pullup resistors
(EN, LATCH)
VCC
RIN
3 Serial output
(S-OUT)
L-GND
VCC
2 Inputs with pulldown resistors
(T, S-IN)
VCC
RIN
4 Parallel outputs
(O1 – O8)
VCC
L-GND
L-GND
P-GND
L-GND





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