Fanout Buffer. AK8181B Datasheet

AK8181B Buffer. Datasheet pdf. Equivalent

Part AK8181B
Description 3.3V LVPECL 1:4 Clock Fanout Buffer
Feature AK8181B 3.3V LVPECL 1:4 Clock Fanout Buffer AK8181B Features Four differential 3.3V LVPECL outputs .
Manufacture Asahi Kasei Microsystems
Datasheet
Download AK8181B Datasheet

AK8181B 3.3V LVPECL 1:4 Clock Fanout Buffer AK8181B Feature AK8181B Datasheet
Recommendation Recommendation Datasheet AK8181B Datasheet




AK8181B
AK8181B
3.3V LVPECL 1:4
Clock Fanout Buffer
AK8181B
Features
Four differential 3.3V LVPECL outputs
Selectable LVTTL/LVCMOS CLK or crystal
input
Clock output frequency up to 266MHz
Output skew : 10ps typical
Part-to-part skew : 200ps maximum
Propagation delay : 1.4ns maximum
Additive phase jitter(RMS) : 0.057ps(typical)
Operating Temperature Range: -40 to +85°C
Package: 20-pin TSSOP (Pb free)
Pin compatible with ICS8535I-31
Description
The AK8181B is a member of AKMLVPECL
clock fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8181B distributes 4 buffered
clocks.
AK8181B are derived from AKMlong-term-
experienced clock device technology, and enable
clock output to perform low skew. The AK8181B
is available in a 20-pin TSSOP package.
Block Diagram
MS1417-E-02
-1-
Dec-2012



AK8181B
AK8181B
Pin Descriptions
Package: 20-Pin TSSOP (Top View)
Pin No.
1
2
3
4
5
6
7
8
9
10
11, 12
13
14, 15
16, 17
18
19, 20
Pin Name
VSS
CLK_EN
CLK_SEL
CLK
NC
XTAL_IN
XTAL_OUT
NC
NC
VDD
Q3n, Q3
VDD
Q2n, Q2
Q1n, Q1
VDD
Q0n, Q0
Pin
Type
PWR
IN
IN
IN
--
IN
OUT
--
--
PWR
OUT
PWR
OUT
OUT
PWR
OUT
Pullup
down
--
Pull up
Pull down
Pull down
--
--
--
--
--
--
--
--
--
--
--
--
Description
Negative power supply
Synchronizing clock output enable (LVCMOS/LVTTL)
Pin is connected to VDD by internal resistor. (typ. 51k
High (Open): clock outputs follow clock input.
Low: Q outputs are forced low, Qn outputs are forced high.
CLK Select Input (LVCMOS/LVTTL)
Pin is connected to VSS by internal resistor. (typ. 51k
High: selects XTAL input Low (Open): selects CLK input
LVCMOS/LVTTL Clock Input
Pin is connected to VSS by internal resistor. (typ. 51k
*When using crystal input (CLK_SEL=High), it should be connected
to VSS or opened.
No connect
Crystal oscillator interface
*When using CLK input (CLK_SEL=Low), it should be connected to
VSS or opened.
Crystal oscillator interface
*When using CLK input (CLK_SEL=Low), it should be connected to
VSS or opened.
No connect
No connect
Positive power supply
Differential clock output (LVPECL)
Positive power supply
Differential clock output (LVPECL)
Differential clock output (LVPECL)
Positive power supply
Differential clock output (LVPECL)
Ordering Information
Part Number
Marking
AK8181B
AK8181B
Shipping
Packaging
Tape and Reel
Package
20-pin TSSOP
Temperature
Range
-40 to 85 °C
Dec-2012
MS1417-E-02
-2-





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