buffer/line driver. 74LVC16244A Datasheet

74LVC16244A driver. Datasheet pdf. Equivalent

74LVC16244A Datasheet
Recommendation 74LVC16244A Datasheet
Part 74LVC16244A
Description 16-bit buffer/line driver
Feature 74LVC16244A; 74LVC16244A; 74LVCH16244A 16-bit buffer/line driver; 5 V input/output tolerant; 3-state Rev. 15 — .
Manufacture nexperia
Datasheet
Download 74LVC16244A Datasheet




nexperia 74LVC16244A
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 15 — 15 February 2019
Product data sheet
1. General description
The 74LVC16244A; 74LVCH16244A are 16-bit non-inverting buffer/line drivers with 3-state bus
compatible outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit
buffer. It features four output enable inputs, (1OE to 4OE) each controlling four of the 3-state
outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to
the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to
hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
High-impedance when VCC = 0 V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C



nexperia 74LVC16244A
Nexperia
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Temperature range Package
Name
74LVC16244ADL
-40 °C to +125 °C SSOP48
74LVCH16244ADL
74LVC16244ADGG
-40 °C to +125 °C TSSOP48
74LVCH16244ADGG
74LVC16244ADGV
-40 °C to +125 °C TSSOP48 [1]
74LVCH16244ADGV
Description
plastic shrink small outline package;
48 leads; body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic thin shrink small outline package;
48 leads; body width 4.4 mm;
lead pitch 0.4 mm
Version
SOT370-1
SOT362-1
SOT480-1
[1] Also known as TVSOP48.
4. Functional diagram
47
1A0
46
1A1
44
1A2
43
1A3
1
1OE
2 36
1Y0 3A0
3 35
1Y1 3A1
5 33
1Y2 3A2
6 32
1Y3 3A3
25
3OE
41
2A0
40
2A1
38
2A2
37
2A3
48
2OE
8 30
2Y0 4A0
9 29
2Y1 4A1
11 27
2Y2 4A2
12 26
2Y3 4A3
24
4OE
Fig. 1. Logic symbol
13
3Y0
14
3Y1
16
3Y2
17
3Y3
19
4Y0
20
4Y1
22
4Y2
23
4Y3
mna996
1OE 1
2OE 48
3OE
4OE
25
24
1A0 47
1A1 46
1A2 44
1A3 43
2A0 41
2A1 40
2A2 38
2A3 37
3A0 36
3A1 35
3A2 33
3A3 32
4A0 30
4A1 29
4A2 27
4A3 26
EN1
EN2
EN3
EN4
11
12
13
14
Fig. 2. IEC logic symbol
2 1Y0
3 1Y1
5 1Y2
6 1Y3
8 2Y0
9 2Y1
11 2Y2
12 2Y3
13 3Y0
14 3Y1
16 3Y2
17 3Y3
19 4Y0
20 4Y1
22 4Y2
23 4Y3
001aae231
VCC
Fig. 3. Bus hold circuit
data input
to internal circuit
mna705
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 15 — 15 February 2019
© Nexperia B.V. 2019. All rights reserved
2 / 14



nexperia 74LVC16244A
Nexperia
5. Pinning information
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
5.1. Pinning
1OE 1
1Y0 2
1Y1 3
GND 4
1Y2 5
1Y3 6
VCC 7
2Y0 8
2Y1 9
GND 10
2Y2 11
2Y3 12
3Y0 13
3Y1 14
GND 15
3Y2 16
3Y3 17
VCC 18
4Y0 19
4Y1 20
GND 21
4Y2 22
4Y3 23
4OE 24
74LVC16244A
74LVCH16244A
48 2OE
47 1A0
46 1A1
45 GND
44 1A2
43 1A3
42 VCC
41 2A0
40 2A1
39 GND
38 2A2
37 2A3
36 3A0
35 3A1
34 GND
33 3A2
32 3A3
31 VCC
30 4A0
29 4A1
28 GND
27 4A2
26 4A3
25 3OE
001aaj052
Fig. 4. Pin configuration SOT370-1 (SSOP48), SOT362-1 (TSSOP48) and SOT480-1 (TSSOP48)
5.2. Pin description
Table 2. Pin description
Symbol
1OE, 2OE, 3OE, 4OE
1Y0 to 1Y3
2Y0 to 2Y3
3Y0 to 3Y3
4Y0 to 4Y3
GND
VCC
1A0 to 1A3
2A0 to 2A3
3A0 to 3A3
4A0 to 4A3
Pin
1, 48, 25, 24
2, 3, 5, 6
8, 9, 11, 12
13, 14, 16, 17
19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
47, 46, 44, 43
41, 40, 38, 37
36, 35, 33, 32
30, 29, 27, 26
Description
output enable input (active LOW)
data output
data output
data output
data output
ground (0 V)
supply voltage
data input
data input
data input
data input
74LVC_LVCH16244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 15 — 15 February 2019
© Nexperia B.V. 2019. All rights reserved
3 / 14







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