Flash Memory. AT49BV008 Datasheet

AT49BV008 Datasheet PDF, Equivalent


Part Number

AT49BV008

Description

8-Megabit 1M x 8 3-volt Only Flash Memory

Manufacture

ATMEL

Total Page 12 Pages
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Download AT49BV008 Datasheet PDF


AT49BV008 Datasheet
Features
Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time - 110 ns
Internal Program Control and Timer
16K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 30 µs/Byte Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV/LV008 is a 3-volt-only in-system Flash Memory device. Its 8 megabits of
memory is organized as 1,024,576 words by 8 bits. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 110 ns
with power dissipation of just 90 mW over the commercial temperature range. When
the device is deselected, the CMOS standby current is less than 50 µA.
(continued)
Pin Configurations
Pin Name
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Data Inputs/Outputs
No Connect
TSOP Top VIew
Type 1
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RDY/BUSY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A17
39 GND
38 NC
37 A19
36 A10
35 I/O7
34 I/O6
33 I/O5
32 I/O4
31 VCC
30 VCC
29 NC
28 I/O3
27 I/O2
26 I/O1
25 I/O0
24 OE
23 GND
22 CE
21 A0
8-Megabit
(1M x 8)
3-volt Only
Flash Memory
AT49BV008
AT49LV008
AT49BV/LV008
8-Megabit 1M x
8 3-volt Only
Rev. 1043A–03/98
1

AT49BV008 Datasheet
To allow for simple in-system reprogrammability, the
AT49BV/LV008 does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV008 is performed by eras-
ing the entire 8 megabits of memory and then programming
on a byte-by-byte basis. The typical byte programming time
is a fast 30 µs. The end of a program cycle can be option-
ally detected by the DATA polling feature. Once the end of
a byte program cycle has been detected, a new access for
a read or program can begin. The typical number of pro-
gram and erase cycles is in excess of 10,000 cycles
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
FFFFFH
03FFFH
00000H
Device Operation
READ: The AT49BV/LV008 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block’s usage as a write protected region is
optional to the user. The address range of the
AT49BV/LV008 boot block is 00000H to 03FFFH.
2 AT49BV/LV008


Features Datasheet pdf Features • Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) • Fast Read Access Time - 110 ns • Internal Program Control and Timer • 16K bytes Boot Block With Lockout • Fast Erase Cycle Time - 10 seconds • Byte-By-Byte Programming - 30 µs/B yte Typical • Hardware Data Protectio n • DATA Polling For End Of Program D etection • Low Power Dissipation – 25 mA Active Current – 50 µA CMOS St andby Current • Typical 10,000 Write Cycles Description The AT49BV/LV008 is a 3-volt-only in-system Flash Memory de vice. Its 8 megabits of memory is organ ized as 1,024,576 words by 8 bits. Manu factured with Atmel’s advanced nonvol atile CMOS technology, the device offer s access times to 110 ns with power dis sipation of just 90 mW over the commerc ial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA. (continued) Pin Configurations Pin Name A0 - A19 CE OE WE RESET RDY/BUSY I/O0 - I/O7 NC Function Addresses Chip Enab.
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