Flash Memory. AT49LV8192A Datasheet

AT49LV8192A Datasheet PDF, Equivalent


Part Number

AT49LV8192A

Description

8-megabit (1M x 8/512K x 16) Flash Memory

Manufacture

ATMEL

Total Page 20 Pages
PDF Download
Download AT49LV8192A Datasheet PDF


AT49LV8192A Datasheet
Features
Single-voltage Read/Write Operation: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time – 70 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Word (16K Bytes) Boot Block with Programming Lockout
– Two 4K Word (8K Bytes) Parameter Blocks
– One 496K Word (992K Bytes) Main Memory Array Block
Fast Sector Erase Time – 10 seconds
Byte-by-byte or Word-by-word Programming – 30 µs Typical
Hardware Data Protection
Data Polling for End of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV008A(T) and AT49BV/LV8192A(T) are 3-volt, 8-megabit Flash memories
organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufac-
tured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access
times to 70 ns with power dissipation of just 67 mW at 2.7V read. When deselected,
the CMOS standby current is less than 50 µA.
Pin Configurations
Pin Name
Function
A0 - A18
CE
OE
Addresses
Chip Enable
Output Enable
WE
RESET
RDY/BUSY
VPP
Write Enable
Reset
Ready/Busy Output
VPP can be left unconnected or connected to VCC, GND, 5V or
12V. The input has no effect on the operation of the device.
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
8-megabit
(1M x 8/
512K x 16)
Flash Memory
AT49BV008A
AT49BV008AT
AT49BV8192A
AT49BV8192AT
AT49LV8192A
AT49LV8192AT
Rev. 1049J–FLASH–05/02
1

AT49LV8192A Datasheet
AT49BV/LV8192A(T) TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE
46 GND
45 I/O15 / A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
AT49BV008A(T) TSOP Top View
Type 1
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
VPP
RDY/BUSY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A17
39 GND
38 NC
37 A-1
36 A10
35 I/O7
34 I/O6
33 I/O5
32 I/O4
31 VCC
30 VCC
29 NC
28 I/O3
27 I/O2
26 I/O1
25 I/O0
24 OE
23 GND
22 CE
21 A0
AT49BV/LV8192A(T)
CBGA Top View (Ball Down)
12345678
A
A13 A11 A8 VPP NC NC A7 A4
B
A14 A10 WE RST A18 A17 A5 A2
C
A15 A12 A9 NC NC A6 A3 A1
D
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE A0
E
BYTE I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND
F
GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
AT49BV008A(T) Standard Pin Definition
CBGA Top View (Ball Down)
12345678
A
A13 A11 A8 VPP NC NC A7 A4
B
A14 A10 WE RST A18 A17 A5 A2
C
A15 A12 A9 NC NC A6 A3 A1
D
A16 NC I/O5 NC I/O2 NC CE A0
E
NC A-1 I/O6 NC I/O3 NC I/O0 GND
F
GND I/O7 NC I/O4 VCC NC I/O1 OE
Note: “•” denotes a white dot on the package.
AT49BV008A(T) Alternate Pin Definition
CBGA Top View (Ball Down)
12345678
A
A14 A12 A8 VPP NC NC A7 A4
B
A15 A10 WE RST A19 A18 A5 A2
C
A16 A13 A9 NC NC A6 A3 A1
D
A17 NC I/O5 NC I/O2 NC CE A0
E
NC A11 I/O6 NC I/O3 NC I/O0 GND
F
GND I/O7 NC I/O4 VCC NC I/O1 OE
The device contains a user-enabled boot blockprotection feature. Two versions of the
feature are available: the AT49BV008A/8192A locates the boot block at lowest order
addresses (bottom boot); the AT49BV008AT/8192AT locates it at highest order
addresses (top boot).
To allow for simple in-system reprogrammability, the AT49BV008A(T)/8192A(T) does
not require high input voltages for programming. Reading data out of the device is simi-
lar to reading from an EPROM; it has standard CE, OE and WE inputs to avoid bus
contention. Reprogramming the AT49BV008A(T)/ 8192A(T) is performed by first erasing
a block of data and then by programming on a byte-by-byte or word-by-word basis.
The device is erased by executing the Erase command sequence; the device internally
controls the erase operation. The memory is divided into four blocks for erase opera-
tions. There are two 4K word parameter block sections, the boot block, and the main
memory array block. The typical number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a reprogramming lock out feature to
provide data integrity. This feature is enabled by a command sequence. Once the boot
block programming lockout feature is enabled, the data in the boot block cannot be
changed when input levels of 5.5 volts or less are used. The boot sector is designed to
contain user secure code.
2 AT49BV008A(T)/8192A(T)
1049J–FLASH–05/02


Features Datasheet pdf Features • Single-voltage Read/Write O peration: 2.7V to 3.6V (BV), 3.0V to 3. 6V (LV) • Fast Read Access Time – 7 0 ns • Internal Erase/Program Control • Sector Architecture – One 8K Wor d (16K Bytes) Boot Block with Programmi ng Lockout – Two 4K Word (8K Bytes) P arameter Blocks – One 496K Word (992K Bytes) Main Memory Array Block • Fas t Sector Erase Time – 10 seconds • Byte-by-byte or Word-by-word Programmin g – 30 µs Typical • Hardware Data Protection • Data Polling for End of Program Detection • Low Power Dissipa tion – 25 mA Active Current – 50 µ A CMOS Standby Current • Typical 10,0 00 Write Cycles Description The AT49B V008A(T) and AT49BV/LV8192A(T) are 3-vo lt, 8-megabit Flash memories organized as 1,048,576 words of 8 bits each or 51 2K words of 16 bits each. Manufactured with Atmel’s advanced nonvolatile CMO S technology, the devices offer access times to 70 ns with power dissipation o f just 67 mW at 2.7V read. When deselected, the CMOS standby cu.
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