Flash Memory. AT49LV020 Datasheet

AT49LV020 Datasheet PDF, Equivalent


Part Number

AT49LV020

Description

2-Megabit (256K x 8) Single 2.7-volt Battery-Voltage Flash Memory

Manufacture

ATMEL

Total Page 10 Pages
PDF Download
Download AT49LV020 Datasheet PDF


AT49LV020 Datasheet
Features
Single Supply Voltage, Range 2.7V to 3.6V
Single Supply for Read and Write
Fast Read Access Time - 70 ns
Internal Program Control and Timer
8K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte By Byte Programming - 30 µs/Byte typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49BV020 and the AT49LV020 are 3-volt-only, 2 megabit Flash memories
organized as 262,144 words of 8 bits each. Manufactured with Atmel's advanced non-
volatile CMOS technology, the devices offer access times to 70 ns with power dissipa-
tion of just 90 mW over the commercial temperature range. When the device is dese-
lected, the CMOS standby current is less than 50 µA.
To allow for simple in-system reprogrammability, the AT49BV/LV020 does not require
high input voltages for programming. Three-volt-only commands determine the read
and programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49BV/LV020 is performed by eras-
ing the entire 2 megabits of memory and then programming on a byte by byte basis.
The typical byte programming time is a fast 30 µs. The end of a program cycle can be
optionally detected by the DATA polling feature. Once the end of a byte program cycle
has been detected, a new access for a read or program can begin. The typical num-
ber of program and erase cycles is in excess of 10,000 cycles.
Pin Configuration
(continued)
Pin Name
A0 - A17
CE
OE
WE
I/O0 - I/O7
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
VSOP Top View (8 x 14mm) or
TSOP Top View (8 x 20mm)
Type 1
PLCC Top View
2-Megabit
(256K x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
AT49BV020
AT49LV020
Rev. 0678C–03/98
1

AT49LV020 Datasheet
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
Device Operation
READ: The AT49BV/LV020 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.
ERASURE: Before a byte can be reprogrammed, the 256K
bytes memory array (or 248K bytes if the boot block fea-
tured is used) must be erased. The erased state of the
memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle oper-
ation (please refer to the Command Definitions table). The
device will automatically generate the required internal pro-
gram pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method. To activate the lockout feature, a series
of six program commands to specific addresses with spe-
cific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
2 AT49BV020


Features Datasheet pdf Features • Single Supply Voltage, Rang e 2.7V to 3.6V • Single Supply for Re ad and Write • Fast Read Access Time - 70 ns • Internal Program Control an d Timer • 8K bytes Boot Block With Lo ckout • Fast Erase Cycle Time - 10 se conds • Byte By Byte Programming - 30 µs/Byte typical • Hardware Data Pro tection • DATA Polling For End Of Pro gram Detection • Low Power Dissipatio n – 25 mA Active Current – 50 µA C MOS Standby Current • Typical 10,000 Write Cycles Description The AT49BV02 0 and the AT49LV020 are 3-volt-only, 2 megabit Flash memories organized as 262 ,144 words of 8 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access t imes to 70 ns with power dissipation of just 90 mW over the commercial tempera ture range. When the device is deselect ed, the CMOS standby current is less th an 50 µA. To allow for simple in-syst em reprogrammability, the AT49BV/LV020 does not require high input voltages for programming. Three-vo.
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