Flash Memory. AT49BV080T Datasheet

AT49BV080T Datasheet PDF, Equivalent


Part Number

AT49BV080T

Description

8-Megabit (1M x 8) Single 2.7-volt Battery-Voltage Flash Memory

Manufacture

ATMEL

Total Page 16 Pages
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Download AT49BV080T Datasheet PDF


AT49BV080T Datasheet
Features
Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV)
Fast Read Access Time - 120 ns
Internal Program Control and Timer
16K Bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 30 µs/Byte Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Small Packaging
– 8 x 14 mm CBGA
Description
The AT49BV/LV080(T) are 3-volt-only in-system Flash Memory devices. Their 8
megabits of memory are organized as 1,024,576 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to
120 ns with power dissipation of just 90 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA.
(continued)
Pin Configurations
Pin Name Function
TSOP Top View
Type 1
A0 - A19
CE
OE
WE
RESET
RDY/BUSY
I/O0 - I/O7
Addresses
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy Output
Data Inputs/Outputs
SOIC
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 NC
39 NC
38 WE
37 OE
36 RDY/BUSY
35 I/O7
34 I/O6
33 I/O5
32 I/O4
31 VCC
30 GND
29 GND
28 I/O3
27 I/O2
26 I/O1
25 I/O0
24 A0
23 A1
22 A2
21 A3
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 VCC
43 CE
42 A12
41 A13
40 A14
39 A15
38 A16
37 A17
36 A18
35 A19
34 NC
33 NC
32 NC
31 NC
30 WE
29 OE
28 RDY/BUSY
27 I/O7
26 I/O6
25 I/O5
24 I/O4
23 VCC
CBGA
Top View
1234567
A
A5 A8 A11 NC A12 A15 A17
B
A4 A7 A10 VCC A13 NC A18
C
A6 A9 RST CE A14 A16 A19
D
A3 I/O1 NC VCC I/O4 I/O7 NC
E
A2 A0 I/O3 GND I/O6 OE NC
F
A1 I/O0 I/O2 GND I/O5 RY/BY WE
8-Megabit
(1M x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
AT49BV080
AT49BV080T
AT49LV080
AT49LV080T
Rev. 0812B–10/98
1

AT49BV080T Datasheet
The device contains a user-enabled “boot block” protection
feature. Two versions of the feature are available: the
AT49BV/LV080 locates the boot block at lowest order
addresses (“bottom boot”); the AT49BVLV080T locates it at
highest order addresses (“top boot”).
To allow for simple in-system reprogrammability, the
AT49BV/LV080(T) does not require high input voltages for
programming. Three-volt-only commands determine the
read and programming operation of the device. Reading
data out of the device is similar to reading from an EPROM.
Reprogramming the AT49BV/LV080 is performed by eras-
ing the entire 8 megabits of memory and then programming
on a byte-by-byte basis. The typical byte programming time
is a fast 30 µs. The end of a program cycle can be option-
ally detected by the DATA polling feature. Once the end of
a byte program cycle has been detected, a new access for
a read or program can begin. The typical number of pro-
gram and erase cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
Block Diagram
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
OE, CE, AND WE
LOGIC
Y DECODER
X DECODER
AT49BV/LV080
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
FFFFFH
04000H
03FFFH
00000H
AT49BV/LV080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(1008K BYTES)
FFFFFH
FC000H
FBFFFH
00000H
Device Operation
READ: The AT49BV/LV080(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in pre-
venting bus contention.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load com-
mands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can con-
vert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indi-
cate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
2 AT49BV/LV080(T)


Features Datasheet pdf Features • Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) • Fast Read Access Time - 120 ns • Internal Program Control and Timer • 16K Bytes Boot Block With Lockout • Fast Erase Cycle Time - 10 seconds • Byte-By-Byte Programming - 30 µs/B yte Typical • Hardware Data Protectio n • DATA Polling For End Of Program D etection • Low Power Dissipation – 25 mA Active Current – 50 µA CMOS St andby Current • Typical 10,000 Write Cycles • Small Packaging – 8 x 14 m m CBGA Description The AT49BV/LV080(T ) are 3-volt-only in-system Flash Memor y devices. Their 8 megabits of memory are organized as 1,024,576 words by 8 b its. Manufactured with Atmel’s advan ced nonvolatile CMOS technology, the de vices offer access times to 120 ns wit h power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS sta ndby current is less than 50 µA. (con tinued) Pin Configurations Pin Name Function TSOP Top View T.
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