Flash Memory. AT49LH002 Datasheet

AT49LH002 Datasheet PDF, Equivalent


Part Number

AT49LH002

Description

2-megabit Firmware Hub and Low-Pin Count Flash Memory

Manufacture

ATMEL

Total Page 30 Pages
PDF Download
Download AT49LH002 Datasheet PDF


AT49LH002 Datasheet
Features
Complies with Intel® Low-Pin Count (LPC) Interface Specification Revision 1.1
– Supports both Firmware Hub (FWH) and LPC Memory Read and Write Cycles
Auto-detection of FWH and LPC Memory Cycles
– Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets
– Can Be Used as LPC Flash for Non-Intel Chipsets
Flexible, Optimized Sectoring for BIOS Applications
– 16-Kbyte Top Boot Sector, Two 8-Kbyte Sectors, One 32-Kbyte Sector,
Three 64-Kbyte Sectors
– Or Memory Array Can Be Divided Into Four Uniform 64-Kbyte Sectors for Erasing
Two Configurable Interfaces
– FWH/LPC Interface for In-System Operation
– Address/Address Multiplexed (A/A Mux) Interface for Programming during
Manufacturing
FWH/LPC Interface
– Operates with the 33 MHz PCI Bus Clock
– 5-signal Communication Interface Supporting Byte Reads and Writes
– Two Hardware Write Protect Pins: TBL for Top Boot Sector and WP for All
Other Sectors
– Five General-purpose Input (GPI) Pins for System Design Flexibility
– Identification (ID) Pins for Multiple Device Selection
– Sector Locking Registers for Individual Sector Read and Write Protection
A/A Mux Interface
– 11-pin Multiplexed Address and 8-pin Data Interface
– Facilitates Fast In-System or Out-of-System Programming
Single Voltage Operation
– 3.0V to 3.6V Supply Voltage for Read and Write Operations
Industry-Standard Package Options
– 32-lead PLCC
– 40-lead TSOP
2-megabit
Firmware Hub
and Low-Pin
Count Flash
Memory
AT49LH002
Description
The AT49LH002 is a Flash memory device designed for use in PC and notebook BIOS
applications. The device complies with version 1.1 of Intel’s LPC Interface Specifica-
tion, providing support for both FWH and LPC memory read and write cycles. The
device can also automatically detect the memory cycle type to allow the AT49LH002
to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.
Pin Configurations
PLCC
TSOP
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
[A3] ID3
[A2] ID2
[A1] ID1
[A0] ID0
[I/O0] FWH0/LAD0
5
6
7
8
9
10
11
12
13
29 IC [IC]
28 GND
27 NC
26 NC
25 VCC
24 INIT [OE]
23 FWH4/LFRAME [WE]
22 RES [RDY/BSY]
21 RES [I/O7]
NC
[IC] IC
NC
NC
NC
NC
[A10] GPI4
NC
[R/C] CLK
VCC
NC
[RST] RST
NC
NC
[A9] GPI3
[A8] GPI2
[A7] GPI1
[A6] GPI0
[A5] WP
[A4] TBL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 GND
39 VCC
38 FWH4/LFRAME [WE]
37 INIT [OE]
36 RES [RDY/BSY]
35 RES [I/O7]
34 RES [I/O6]
33 RES [I/O5]
32 RES [I/O4]
31 VCC
30 GND
29 GND
28 FWH3/LAD3 [I/O3]
27 FWH2/LAD2 [I/O2]
26 FWH1/LAD1 [I/O1]
25 FWH0/LAD0 [I/O0]
24 ID0 [A0]
23 ID1 [A1]
22 ID2 [A2]
21 ID3 [A3]
Note: [ ] Designates A/A Mux Interface.
3377B–FLASH–9/03
1

AT49LH002 Datasheet
Block Diagram
The sectoring of the AT49LH002’s memory array has been optimized to meet the needs of
today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space
can be used more efficiently. Because certain BIOS code modules must reside in their own
sectors by themselves, the wasted and unused memory space that occurred with previous
generation BIOS Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional BIOS routines to be developed and added while still main-
taining the same overall device density.
The memory array of the AT49LH002 can be sectored in two ways simply by using two differ-
ent erase commands. Using one erase command allows the device to contain a total of seven
sectors comprised of a 16-Kbyte boot sector, two 8-Kbyte sectors, a 32-Kbyte sector, and
three 64-Kbyte sectors. The 16-Kbyte boot sector is located at the top (uppermost) of the
device’s memory address space and can be hardware write protected by using the TBL pin.
Alternatively, by using a different erase command, the memory array can be arranged into four
even erase sectors of 64-Kbyte each, allowing the top 64-Kbyte region to be used as the boot
sector. The TBL pin, when used with the second erase command, will hardware write protect
the entire top 64-Kbyte region against erasure.
The AT49LH002 supports two hardware interfaces: The FWH/LPC interface for In-System
operations and the A/A Mux interface for programming during manufacturing. The Interface
Configuration (IC) pin of the device provides the control between these two interfaces. An
internal Command User Interface (CUI) serves as the control center between the device inter-
faces and the internal operation of the nonvolatile memory. A valid command sequence
written to the CUI initiates device automation.
Specifically designed for use in 3-volt systems, the AT49LH002 supports read, program, and
erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required
for programming and erasing.
The AT49LH002 utilizes fixed program and erase times, independent of the number of pro-
gram and erase cycles that have occurred. Therefore, the system does not need to be
calibrated or correlated to the cumulative number of program and erase cycles.
TBL WP INIT
CLK
FWH4/LFRAME
FWH/LAD[3:0]
ID[3:0]
GPI[4:0]
IC
RST
R/C
A[10:0]
I/O[7:0]
OE
WE
RDY/BSY
FWH/LPC
INTERFACE
INTERFACE CONTROL
AND LOGIC
A/A MUX
INTERFACE
CONTROL LOGIC
Y-DECODER
X-DECODER
I/O BUFFERS
AND LATCHES
Y-GATING
FLASH
MEMORY
ARRAY
2 AT49LH002
3377B–FLASH–9/03


Features Datasheet pdf Features • Complies with Intel® Low-P in Count (LPC) Interface Specification Revision 1.1 – Supports both Firmware Hub (FWH) and LPC Memory Read and Writ e Cycles • Auto-detection of FWH and LPC Memory Cycles – Can Be Used as FW H for Intel 8xx, E7xxx, and E8xxx Serie s Chipsets – Can Be Used as LPC Flash for Non-Intel Chipsets • Flexible, O ptimized Sectoring for BIOS Application s – 16-Kbyte Top Boot Sector, Two 8-K byte Sectors, One 32-Kbyte Sector, Thre e 64-Kbyte Sectors – Or Memory Array Can Be Divided Into Four Uniform 64-Kby te Sectors for Erasing • Two Configur able Interfaces – FWH/LPC Interface f or In-System Operation – Address/Addr ess Multiplexed (A/A Mux) Interface for Programming during Manufacturing • F WH/LPC Interface – Operates with the 33 MHz PCI Bus Clock – 5-signal Commu nication Interface Supporting Byte Read s and Writes – Two Hardware Write Pro tect Pins: TBL for Top Boot Sector and WP for All Other Sectors – Five General-purpose Input (GPI) P.
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