Only DataFlash. AT45DB161B Datasheet

AT45DB161B DataFlash. Datasheet pdf. Equivalent

AT45DB161B Datasheet
Recommendation AT45DB161B Datasheet
Part AT45DB161B
Description 16-megabit 2.5-volt Only or 2.7-volt Only DataFlash
Feature AT45DB161B; Features • Single 2.5V - 3.6V or 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible •.
Manufacture ATMEL
Datasheet
Download AT45DB161B Datasheet




ATMEL AT45DB161B
Features
Single 2.5V - 3.6V or 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
20 MHz Max Clock Frequency
Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 4096 Pages (528 Bytes/Page) Main Memory
Supports Page and Block Erase Operations
Two 528-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
Hardware Data Protection Feature
100% Compatible to AT45DB161
5.0V-tolerant Inputs: SI, SCK, CS, RESET and WP Pins
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Options
Description
The AT45DB161B is a 2.5-volt or 2.7-volt only, serial interface Flash memory ideally
suited for a wide variety of digital voice-, image-, program code- and data-storage
Pin Configurations
Pin Name
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
Function
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
DataFlash Card(1)
Top View through Package
7654321
TSOP Top View – Type 1
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
SOIC
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 NC
26 NC
25 WP
24 RESET
23 RDY/BUSY
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
CBGA Top View
through Package
12345
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS RDY/BSY WP NC
D
NC SO SI RESET NC
E
NC NC NC NC NC
16-megabit
2.5-volt Only or
2.7-volt Only
DataFlash®
AT45DB161B
Note: 1. See AT45DCB002 Datasheet.
CASON – Top View through Package
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
Rev. 2224I–DFLSH–10/04
1



ATMEL AT45DB161B
Block Diagram
applications. Its 17,301,504 bits of memory are organized as 4096 pages of 528 bytes
each. In addition to the main memory, the AT45DB161B also contains two SRAM
data buffers of 528 bytes each. The buffers allow receiving of data while a page in the
main memory is being reprogrammed, as well as writing a continuous data stream.
EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three
step Read-Modify-Write operation.Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses a SPI serial interface to sequentially access its data. DataFlash supports SPI mode
0 and mode 3. The simple serial interface facilitates hardware layout, increases system
reliability, minimizes switching noise, and reduces package size and active pin count.
The device is optimized for use in many commercial and industrial applications where
high density, low pin count, low voltage, and low power are essential. The device oper-
ates at clock frequencies up to 20 MHz with a typical active read current consumption of
4 mA.
To allow for simple in-system reprogrammability, the AT45DB161B does not require
high input voltages for programming. The device operates from a single power supply,
2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The
AT45DB161B is enabled through the chip select pin (CS) and accessed via a three-wire
interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock
(SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming.
When the device is shipped from Atmel, the most significant page of the memory array
may not be erased. In other words, the contents of the last page may not be filled with
FFH.
WP FLASH MEMORY ARRAY
PAGE (528 BYTES)
Memory Array
BUFFER 1 (528 BYTES)
BUFFER 2 (528 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI SO
To provide optimal flexibility, the memory array of the AT45DB161B is divided into three
levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture
Diagram illustrates the breakdown of each level and details the number of pages per
sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
2 AT45DB161B
2224I–DFLSH–10/04



ATMEL AT45DB161B
AT45DB161B
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages
4,224 bytes (4K + 128)
SECTOR 1 = 248 Pages
130,944 bytes (124K + 3,968)
SECTOR 0
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
SECTOR 2 = 256 Pages
135,168 bytes (128K + 4K)
SECTOR 3 = 256 Pages
135,168 bytes (128K + 4K)
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 66
8 Pages
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 16 = 256 Pages
135,168 bytes (128K + 4K)
Device Operation
Read Commands
2224I–DFLSH–10/04
BLOCK 509
BLOCK 510
BLOCK 511
Block = 4224 bytes
(4K + 128)
PAGE 4093
PAGE 4094
PAGE 4095
Page = 528 bytes
(512 + 16)
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main
memory address location through the SI (serial input) pin. All instructions, addresses
and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to
denote the ten address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA11 - PA0 and BA9 - BA0
where PA11 - PA0 denotes the 12 address bits required to designate a page address
and BA9 - BA0 denotes the ten address bits required to designate a byte address within
the page.
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 10 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
3







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