Flash Memory. Am29F002NT Datasheet

Am29F002NT Memory. Datasheet pdf. Equivalent

Am29F002NT Datasheet
Recommendation Am29F002NT Datasheet
Part Am29F002NT
Description 2 Megabit CMOS 5.0 Volt-only Sector Architecture Flash Memory
Feature Am29F002NT; PRELIMINARY Am29F002NT/Am29F002NB 2 Megabit (262,144 x 8-Bit) CMOS 5.0 Volt-only, Sector Architectu.
Manufacture AMD
Datasheet
Download Am29F002NT Datasheet




AMD Am29F002NT
PRELIMINARY
Am29F002NT/Am29F002NB
2 Megabit (262,144 x 8-Bit)
CMOS 5.0 Volt-only, Sector Architecture Flash Memory
DISTINCTIVE CHARACTERISTICS
5.0 V ± 10% for read and write operations
— Minimizes system-level power requirements
Compatible with JEDEC-standard commands
— Pinout and software compatible with single-
power-supply flash standards
— Superior inadvertent write protection
Package options
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
Minimum 100,000 write erase cycles guaranteed
High performance
— Access times as fast as 55 ns
Sector architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
three 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
Embedded Erase Algorithm
— Automatically pre-programs and erases the chip
or any sector
Embedded Program Algorithm
— Automatically programs and verifies data at a
specified address
Data Polling and Toggle Bit feature
— Detects program or erase cycle completion
Erase Suspend/Resume
— Supports reading data from or programming
data to a sector not being erased
Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
Enhanced power management for standby
mode
— 400 μA typical TTL standby current
— 1 μA typical CMOS standby current
— Standard access time from standby modes
Boot code sector architecture
— T = Top sector
— B = Bottom sector
Low VCC write inhibit 3.2 V
GENERAL DESCRIPTION
The Am29F002N is a 2 Mbit, 5.0 Volt-only Flash
memory organized as 256 Kbytes of 8 bits each. The 2
Mbits of data is divided into 7 sectors of one 16 Kbyte,
two 8 Kbyte, one 32 Kbyte, and three 64 Kbytes, for
flexible erase capability. The 8 bits of data appear on
DQ0-DQ7. The Am29F002N is offered in a 32-pin
PDIP, PLCC, and TSOP packages. This device is
designed to be programmed in-system with the stan-
dard system 5.0 Volt VCC supply. A power supply pro-
viding 12.0 Volt VPP is not required for program or
erase operations. The device can also be repro-
grammed in standard EPROM programmers.
The standard Am29F002N offers access times of 55
ns, 70 ns, 90 ns, and 120 ns, allowing high speed
microprocessors to operate without wait states. To
eliminate bus contention, the device has separate chip
enable (CE), write enable (WE), and output enable
(OE) controls.
The Am29F002N is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine, which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from 12.0
Volt Flash or EPROM devices.
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 21166 Rev: A Amendment/0
Issue Date: December 1996



AMD Am29F002NT
PRELIMINARY
The Am29F002N is programmed by executing the
program command sequence, which invokes the
Embedded Program Algorithm. This internal algo-
rithm automatically times the program pulse widths
and verifies proper cell margin. The Am29F002N is
erased by executing the erase command sequence,
which invokes the Embedded Erase Algorithm.
Before executing the erase operation, this internal
algorithm automatically preprograms the array if it is
not already programmed. During erase, the device
automatically times the erase pulse widths and veri-
fies proper cell margin.
This device also features a sector erase architecture,
which allows sectors of memory to be erased and
reprogrammed without affecting the data contents of
other sectors. A sector is typically erased and verified
within one second if already pre-programmed. The
Am29F002N is erased when shipped from the factory.
The Am29F002N also features hardware sector pro-
tection. This feature disables both program and
erase operations in any combination of the seven
sectors of memory.
AMD has implemented an Erase Suspend/Resume
feature that enables the user to put erase on hold for
any period of time to read data from or program data to
a sector not being erased. Thus, true background
erase can be achieved.
The device features single 5.0 Volt power supply oper-
ation for both read and write functions.
Internally generated and regulated voltages are pro-
vided for the program and erase operations. A low VCC
detector automatically inhibits write operations when a
loss of device power occurs. The end of program or
erase is detected by Data Polling of DQ7, or by the
Toggle Bit (DQ6). Once the end of a program or erase
cycle has been completed, the device automatically
resets to the read mode.
The Am29F002N memory electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a
time using the EPROM programming mechanism of
hot electron injection. AMD's Flash technology com-
bines years of Flash memory manufacturing experi-
ence to produce the highest levels of quality, reliability
and cost effectiveness.
FLEXIBLE SECTOR ARCHITECTURE
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three
64 Kbyte sectors
Individual-sector or multiple-sector erase capability
Sector protection is user definable
Sector
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Sector Size
16 Kbytes
8 Kbytes
8 Kbytes
32 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
Address Range
3C000h-3FFFFh
3A000h-3BFFFh
38000h-39FFFh
30000h-37FFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
Am29F002NT Sector Architecture
Notes:
Refer to Table 3 and Table 4 for a more information on addresses.
Sector
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Sector Size
64 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
Address Range
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
Am29F002NB Sector Architecture
2 Am29F002NT/Am29F002NB



AMD Am29F002NT
PRODUCT SELECTOR GUIDE
Family Part No:
Ordering Part No: VCC = 5.0 V ± 5%
VCC = 5.0 V ± 10%
Max Access Time (ns)
CE Access (ns)
OE Access (ns)
PRELIMINARY
Am29F002N
-55
-70 -90
55 70 90
55 70 90
30 30 35
-120
120
120
50
BLOCK DIAGRAM
VCC
VSS
WE
CE
OE
State
Control
Command
Register
Erase Voltage
Generator
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
DQ0–DQ7
Input/Output
Buffers
Data Latch
VCC Detector
A0–A17
Timer
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
21166A-1
Am29F002NT/Am29F002NB
3







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