Flash Memory. Am29F100B Datasheet

Am29F100B Memory. Datasheet pdf. Equivalent

Am29F100B Datasheet
Recommendation Am29F100B Datasheet
Part Am29F100B
Description 1 Megabit CMOS 5.0 Volt-only Sector Erase Flash Memory
Feature Am29F100B; 5.0 V-only Flash FINAL Am29F100T/Am29F100B 1 Megabit (131,072 x 8-bit/65,536 x 16-bit) CMOS 5.0 Vo.
Manufacture AMD
Datasheet
Download Am29F100B Datasheet




AMD Am29F100B
FINAL
Am29F100T/Am29F100B
1 Megabit (131,072 x 8-bit/65,536 x 16-bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s 5.0 V ± 10% for read and write operations
— Minimizes system level power requirements
s Compatible with JEDEC-standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s Package options
— 44-pin SO
— 48-pin TSOP
s Minimum 100,000 write/erase cycles guaranteed
s High performance
— 70 ns maximum access time
s Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
one 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
s Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
s Embedded EraseAlgorithms
— Automatically pre-programs and erases the chip
or any sector
s Embedded ProgramAlgorithms
— Automatically programs and verifies data at
specified address
s Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
s Erase Suspend/Resume
— Supports reading data from a sector not being
erased
s Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
s Enhanced power management for standby
mode
— 25 µA typical standby current
s Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
s Hardware RESET pin
— Resets internal state machine to the read mode
GENERAL DESCRIPTION
The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory
organized as 128 Kbytes of 8 bits each or 64 words of
16 bits each. The 1 Mbit of data is divided into 5 sectors
of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and one
64 Kbytes, for flexible erase capability. The 8 bits of
data will appear on DQ0-DQ7 or 16 bits on DQ0-DQ15.
The Am29F100 is offered in 44-pin SO and 48-pin
TSOP packages. This device is designed to be pro-
grammed in-system with the standard system 5.0 Volt
VCC supply. 12.0 Volt VPP is not required for program
or erase operations. The device can also be repro-
grammed in standard EPROM programmers.
The standard Am29F100 offers access times of 70 ns,
90 ns, 120 ns, and 150 ns, allowing operation of
high-speed microprocessors without wait states. To
eliminate bus contention the device has separate chip
enable (CE), write enable (WE) and output enable (OE)
controls.
The Am29F100 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
Publication# 18926 Rev: B Amendment/+1
Issue Date: April 1997



AMD Am29F100B
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from 12.0
Volt Flash or EPROM devices.
The Am29F100 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This will in-
voke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the device automat-
ically times the erase pulse widths and verifies proper
cell margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F100 is erased when
shipped from the factory.
The Am29F100 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of eleven sectors
of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from a sector that was not being
erased. Thus, true background erase can be achieved.
The device features single 5.0 Volt power supply oper-
ation for both read and write functions. Internally gen-
erated and regulated voltages are provided for the
program and erase operations. A low VCC detector au-
tomatically inhibits write operations during power tran-
sitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29F100 also has a hardware RESET pin. When
this pin is driven low, execution of any Embedded Pro-
gram Algorithm or Embedded Erase Algorithm will be
terminated. The internal state machine will then be
reset into the read mode. The RESET pin may be tied
to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need re-writing after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29F100 memory electrically erases all
b i t s w i t h i n a s e c t o r s i mu l t a n e o u s l y v i a
Fowler-Nordhiem tunneling. The bytes/words are pro-
grammed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
s One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and one
64 Kbyte sectors
s Individual-sector or multiple-sector erase capability
s Sector protection is user definable
SA4
SA3
SA2
SA1
SA 0
16 Kbyte
8 Kbyte
8 Kbyte
32 Kbyte
64 Kbyte
(x8)
1FFFFh
1BFFFFh
19FFFh
17FFFh
0FFFFh
00000h
(x16)
0FFFFh
0DFFFh
0CFFFh
0BFFFh
07FFFh
00000h
18926B-1
Am29F100T Sector Architecture
SA4
SA3
SA2
SA1
SA 0
64 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
(x8)
1FFFh
0FFFFh
07FFFh
05FFFh
03FFFh
00000h
(x16)
0FFFFh
07FFFh
03FFFh
02FFFh
01FFFh
00000h
18926B-2
Am29F100B Sector Architecture
2 Am29F100T/Am29F100B



AMD Am29F100B
PRODUCT SELECTOR GUIDE
Family Part No.
Ordering Part No: VCC = 5.0 V ± 10%
Max Access Time (ns)
CE Access (ns)
OE Access (ns)
-70
70
70
30
BLOCK DIAGRAM
VCC
RY/BY
Buffer
RY/BY
VSS Erase Voltage
Generator
Am29F100
-90 -120
90 120
90 120
35 50
-150
150
150
55
DQ0DQ15
Input/Output
Buffers
WE
BYTE
RESET
CE
OE
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
STB Latch
VCC Detector
A0–A15
A-1
Timer
Y-Decoder
STB
X-Decoder
Y-Gating
Cell Matrix
18926B-3
Am29F100T/Am29F100B
3







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