Document
a
ADSP-2100 Family DSP Microcomputers
ADSP-21xx
SUMMARY 16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter Single-Cycle Instruction Execution & Multifunction
Instructions On-Chip Program Memory RAM or ROM
& Data Memory RAM Integrated I/O Peripherals: Serial Ports, Timer,
Host Interface Port (ADSP-2111 Only)
FEATURES 25 MIPS, 40 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data
(Three-Bus Performance) Dual Data Address Generators with Modulo and
Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM ) Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operat.