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STD8N80K5 Dataheets PDF



Part Number STD8N80K5
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description N-channel Power MOSFET
Datasheet STD8N80K5 DatasheetSTD8N80K5 Datasheet (PDF)

STD8N80K5 Datasheet N-channel 800 V, 0.8 Ω typ., 6 A MDmesh K5 Power MOSFET in a DPAK package TAB 23 1 DPAK D(2, TAB) G(1) S(3) Features Order code VDS RDS(on) max. ID STD8N80K5 800 V 0.95 Ω 6A • Industry’s lowest RDS(on) x area • Industry’s best FoM (figure of merit) • Ultra-low gate charge • 100% avalanche tested • Zener-protected PTOT 110 W Applications • Switching applications AM01476v1_tab Description This very high voltage N-channel Power MOSFET is designed using MDmes.

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STD8N80K5 Datasheet N-channel 800 V, 0.8 Ω typ., 6 A MDmesh K5 Power MOSFET in a DPAK package TAB 23 1 DPAK D(2, TAB) G(1) S(3) Features Order code VDS RDS(on) max. ID STD8N80K5 800 V 0.95 Ω 6A • Industry’s lowest RDS(on) x area • Industry’s best FoM (figure of merit) • Ultra-low gate charge • 100% avalanche tested • Zener-protected PTOT 110 W Applications • Switching applications AM01476v1_tab Description This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Product status links STD8N80K5 Product summary Order code STD8N80K5 Marking 8N80K5 Package DPAK Packing Tape and reel DS9561 - Rev 4 - May 2023 For further information contact your local STMicroelectronics sales office. www.st.com 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter VGS Gate-source voltage ID Drain current (continuous) at TC = 25 °C ID Drain current (continuous) at TC = 100 °C IDM (1) Drain current pulsed PTOT Total power dissipation at TC = 25 °C dv/dt (2) Peak diode recovery voltage slope dv/dt (3) MOSFET dv/dt ruggedness Tj Operating junction temperature range Tstg Storage temperature range 1. Pulse width limited by safe operating area. 2. ISD≤ 6 A, di/dt ≤ 100 A/μs; VDS (peak) ≤ V(BR)DSS 3. VDS ≤ 640 V Table 2. Thermal data Symbol Parameter RthJC Thermal resistance, junction-to-case RthJA (1) Thermal resistance, junction-to-ambient 1. When mounted on 1inch² FR-4 board, 2 oz Cu Symbol IAR EAS Table 3. Avalanche characteristics Parameter Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax.) Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) STD8N80K5 Electrical ratings Value ±30 6 4 24 110 4.5 50 - 55 to 150 Unit V A A A W V/ns °C Value 1.14 50 Unit °C/W °C/W Value Unit 2 A 114 mJ DS9561 - Rev 4 page 2/18 STD8N80K5 Electrical characteristics 2 Electrical characteristics TC = 25 °C unless otherwise specified. Table 4. On/off-state Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA IDSS IGSS VGS(th) RDS(on) Zero gate voltage drain current Gate body leakage current Gate threshold voltage Static drain-source onresistance VGS = 0 V, VDS = 800 V VGS = 0 V, VDS = 800 V TC = 125 °C (1) VDS = 0 V, VGS = ±20 V VDS = VGS, ID = 100 µA VGS = 10 V, ID = 3 A 1. Specified by design, not tested in production. Min. Typ. Max. Unit 800 V 1 µA 50 µA ±10 µA 3 4 5 V 0.8 0.95 Ω Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 450 - pF - 50 - pF - 1 - pF Co(tr) (1) Equivalent capacitance time related - 57 - pF VDS = 0 to 640 V, VGS = 0 V Co(er) (2) Equivalent capacitance energy related 24 - pF Rg Intrinsic gate resistance f = 1 MHz , ID = 0 A - 6 - Ω Qg Total gate charge VDD = 640 V, ID = 6 A - 16.5 - nC Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 to 10 V - 3.2 - nC (see Figure 15. Test circuit for gate charge behavior ) - 11 - nC 1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. Symbol td(on) tr td(off) tf Parameter Turn-on delay time Rise time Turn-off delay time Fall time Table 6. Switching times Test conditions Min. Typ. Max. Unit VDD = 400 V, ID = 3 A, - 12 - ns RG = 4.7 Ω, VGS = 10 V (see Figure 14. Test circuit for - 14 - ns resistive load switching times - 32 - ns and Figure 19. Switching time waveform) - 20 - ns DS9561 - Rev 4 page 3/18 STD8N80K5 Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions ISD Source-drain current ISDM (1) Source-drain current (pulsed) VSD (2) trr Qrr IRRM Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 6 A, VGS = 0 V ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V, see Figure 16. Test circuit for inductive load switching and diode recovery times) trr Qrr IRRM Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16. Test circuit for inductive load switching and diode recovery times) 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%. Min. - - - - Typ. 300 3 20 415 3.8 18 Max. 6 24 1.5 Unit A A V ns µC A ns µC A DS9561 - Rev 4 page 4/18 2.1 Electrical characteri.


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