CY7C008

25/0251 CY7C008/009 CY7C018/019 Features True Dual-Ported memory cells which allow simultaneous access of the same memory location 64K x 8 organization (CY7C008) 128K x 8 organization (CY7C009) 64K x 9 organization (CY7C018) 128K x 9 organization (CY7C019) 0.35-micron CMOS for optimum speed/power High-speed access: 12[1]/15/20 ns Low operating power — Active: ICC = 180 mA (typical) — Standby: ISB3 = 0.05 mA (typical) Logic Block Diagram R/WL CE0L CE1L OEL CEL 64K/128K x 8/9 Dual-Port Static RAM Fully asynchronous operation Automatic power-down Expandable data bus to 16/18 bits or more using Mas- ter/Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports INT flags for port-to-port communication Dual Chip Enables Pin select for Master or Slave Commercial and Industrial temperature ranges Available in 100-pin TQFP Pin-c...