Document
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple 4-3-3-Input NOR Gate
The MC10106 is a triple 4–3–3 input NOR gate.
PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
4 5
3 6 7 9 10 2 11 12 13 15 14
VCC1 = PIN 1 VCC2 = PIN 16
VEE = PIN 8
MC10106
L SUFFIX CERAMIC PACKAGE
CASE 620–10
P SUFFIX PLASTIC PACKAGE
CASE 648–08
FN SUFFIX PLCC
CASE 775–02
DIP PIN ASSIGNMENT
VCC1 BOUT AOUT
AIN AIN AIN AIN VEE
1 2 3 4 5 6 7 8
16 VCC2 15 COUT 14 CIN 13 CIN 12 CIN 11 BIN 10 BIN 9 BIN
Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
3–26
REV 5
MC10106
ELECTRICAL CHARACTERISTICS
Characteristic Power Supply Drain Current Input Current
Output Voltage
Logic 1
Symbol
IE IinH IinL VOH
Output Voltage
Logic 0 VOL
Threshold Voltage Logic 1 VOHA
Threshold Voltage Logic 0 VOLA
Switching Times (50Ω Load) .