Document
Philips Semiconductors
Product specification
TrenchMOS transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope available in TO220AB and SOT404 . Using ’trench’ technology which features very low on-state resistance. It is intended for use in automotive and general purpose switching applications.
BUK95180-100A BUK96180-100A
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. 100 11 54 175 180 173 UNIT V A W ˚C mΩ mΩ
PINNING TO220AB & SOT404
PIN 1 2 3 DESCRIPTION gate drain
2
mb tab
PIN CONFIGURATION
SYMBOL
d
g
3 SOT404 BUK96180-100A
source
1
tab/mb drain
1 2 3 TO220AB BUK95180-100A
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg, Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 100 100 15 11 7.7 44 54 175 UNIT V V V A A A W ˚C
THERMAL RESISTANCES
SYMBOL Rth j-mb Rth j-a Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient(TO220AB) Thermal resistance junction to ambient(SOT404) CONDITIONS in free air Minimum footprint, FR4 board TYP. 60 50 MAX. 2.8 UNIT K/W K/W K/W
May 2000
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor Logic level FET
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C VDS = 100 V; VGS = 0 V; VGS = ±10 V; VDS = 0 V VGS = 5 V; ID = 5 A VGS = 10 V; ID = 5 A VGS = 4.5 V; ID = 5 A Tj = 175˚C Tj = 175˚C MIN. 100 89 1 0.5 -
BUK95180-100A BUK96180-100A
TYP. 1.5 0.05 2 165 152 170
MAX. 2.0 2.3 10 500 100 180 450 173 200
UNIT V V V V V µA µA nA mΩ mΩ mΩ mΩ
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified SYMBOL Ciss Coss Crss td on tr td off tf Ld Ld Ld Ls PARAMETER Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. TYP. 464 60 37 9 112 18 25 4.5 3.5 2.5 7.5 MAX. 619 72 50 20 157 27 38 UNIT pF pF pF ns ns ns ns nH nH nH nH
VDD = 30 V; Rload =1.2Ω; VGS = 5 V; RG = 10 Ω
Measured from drain lead 6 mm from package to centre of die Measured from contact screw on tab to centre of die(TO220AB) Measured from upper edge of drain tab to centre of die(SOT404) Measured from source lead to source bond pad
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 5 A; VGS = 0 V IF = 11 A; VGS = 0 V IF = 11 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V TYP. 0.85 1.1 49 0.13 MAX. 11 44 1.2 UNIT A A V V ns µC
May 2000
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL W
1 DSS
BUK95180-100A BUK96180-100A
PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy
CONDITIONS ID = 5.5 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
MIN. -
TYP. -
MAX. 1.5
UNIT mJ
!
120 110 100 90 80 70 60 50 40 30 20 10 0
PD%
Normalised Power Derating
100
ID/A
RDS(ON)=VSD/ID
10
DC
1
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.1
1
10
VSD/V
100
1000
Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
ID% Normalised Current Derating
Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp
120 110 100 90 80 70 60 50 40 30 20 10 0
Zth/(K/W) 10
0.5
1
0.2 0.1 0.05
0.1
0.02
0.01
0
0
20
40
60
80 100 Tmb / C
120
140
160
180
0.001 1E-07
1E-05
t/s
1E-03
1E-01
1E+01
Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
1 For maximum permissible repetive avalanche current see fig.18. May 2000 3 Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor Logic level FET
BUK95180-100A BUK96180-100A
25 ID/A 20 15 10 5 0 0 2 4 VDS/V 6
VGS/V = 10.0 5.0 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 8 10
12 ID/A 10 8 6 4 .