High-performance EE PLD
Features
• High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 128 Macrocells – 5 ...
Description
Features
High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 128 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 84, 100, 160 Pins – 7.5 ns Maximum Pin-to-pin Delay – Registered Operation up to 125 MHz – Enhanced Routing Resources
Flexible Logic Macrocell – D/T/Latch Configured Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features – Automatic 10 µA Standby for “L” Version – Pin-controlled 1 mA Standby Mode – Programmable Pin-keeper Inputs and I/Os – Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages Advanced EE T...
Similar Datasheet