DSP56303

Freescale Semiconductor Technical Data DSP56303 Rev. 11, 2/2005 DSP56303 24-Bit Digital Signal Processor 16 6 6 3 Triple Timer HI08 ESSI SCI Address Generation Unit Six-Channel DMA Unit Bootstrap ROM Peripheral Expansion Area EXTAL XTAL Internal Data Bus Switch Clock Generator PLL Program Interrupt Controller Program Decode Controller 2 RESET PINIT/NMI MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD PIO_EB PM_EB XM_EB YM_EB Memory Expansion Area PrograM RAM 4096 × 24 bits (default) X Data RAM 2048 × 24 bits (default) Y Data RAM 2048 × 24 bits (default) YAB XAB PAB DAB External 18 Address Bus Switch Address 24-Bit DSP56300 Core DDB YDB XDB PDB GDB External Bus 13 Interface and Inst. Cache Control Control External Data Bus Switch 24 Data Program Address Generator Power Management Data ALU 24 × 24 + 56 →56-bit MAC JTAG Two 56-bit Accumulators 56-bit Barrel Shifter OnCE™ 5 DE Figure 1. DSP56303 Block Diagram The DSP56303 is intended for use in tel...