DSP56311

Freescale Semiconductor Technical Data DSP56311 Rev. 8, 2/2005 DSP56311 24-Bit Digital Signal Processor 3 16 6 6 Memory Expansion Area SCI Triple Timer Address Generation Unit Six Channel DMA Unit Bootstrap ROM Internal Data Bus Switch PIO_EB PM_EB XM_EB YM_EB HI08 ESSI EFCOP Peripheral Expansion Area Program RAM 32 K × 24 bits or 31 K × 24 bits and Instruction Cache 1024 × 24 bits X Data RAM 48 K × 24 bits Y Data RAM 48 K × 24 bits YAB XAB PAB DAB 24-Bit DSP56300 Core DDB YDB XDB PDB GDB External Address Bus Switch 18 Address External Bus Interface and I - Cache Control 13 Control External Data Bus Switch 24 Data Clock Generator PLL Program Interrupt Controller EXTAL XTAL RESET PINIT/NMI PCAP Program Decode Controller MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Program Address Generator Power Management Data ALU 24 × 24 + 56 →56-bit MAC Two 56-bit Accumulators JTAG 56-bit Barrel Shifter OnCE™ 5 DE Figure 1. DSP56311 Block Diagram The DSP5631...