D Flip-Flop. MC74ACT175 Datasheet

MC74ACT175 Flip-Flop. Datasheet pdf. Equivalent

Part MC74ACT175
Description Quad D Flip-Flop
Feature MC74AC175 MC74ACT175 Quad D FlipĆFlop With Master Reset The MC74AC/ACT175 is a high-speed quad D fl.
Manufacture Motorola
Datasheet
Download MC74ACT175 Datasheet



MC74ACT175
MC74AC175
MC74ACT175
Quad D FlipĆFlop With
Master Reset
The MC74AC/ACT175 is a high-speed quad D flip-flop. The device is useful for
general flip-flop requirements where clock and clear inputs are common. The
information on the D inputs is transferred to storage during the LOW-to-HIGH clock
transition. The device has a Master Reset to simultaneously clear all flip-flops, when
MR is low.
The MC74AC/ACT175 consists of four edge-triggered D flip-flops with individual
D inputs and Q and Q outputs. The Clock (CP) and Master Reset (MR) are common
to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master
Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The MC74AC/ACT175 is useful for applications where the Clock and
Master Reset are common to all storage elements.
Outputs Source/Sink 24 mA
• ′ACT175 Has TTL Compatible Inputs
QUAD D FLIP-FLOP
WITH MASTER RESET
N SUFFIX
CASE 648-08
PLASTIC
Pinout: 16-Lead Packages (Top View)
VCC Q3 Q3 D3 D2 Q2 Q2 CP
16 15 14 13 12 11 10 9
12345678
MR Q0 Q0 D0 D1 Q1 Q1 GND
PIN NAMES
D0 – D3
CP
MR
Q0 – Q3
Q0 – Q3
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Outputs
D SUFFIX
CASE 751B-05
PLASTIC
LOGIC SYMBOL
TRUTH TABLE
Inputs
Outputs
MR CP D Qn Qn
LXXLH
H HHL
H LLH
H L X Qn Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition of Clock
D0 D1 D2 D3
CP
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
FACT DATA
5-1



MC74ACT175
MR CP D3
MC74AC175 MC74ACT175
LOGIC DIAGRAM
D2 D1
D0
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
DQ
CP Q
CD
Q3 Q3
Q2 Q2
Q1 Q1
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Q0 Q0
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Vin
Vout
Iin
Iout
ICC
Tstg
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC VCC or GND Current per Output Pin
Storage Temperature
–0.5 to +7.0
–0.5 to VCC + 0.5
–0.5 to VCC + 0.5
± 20
± 50
± 50
–65 to +150
V
V
V
mA
mA
mA
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min Typ
VCC
Supply Voltage
AC
ACT
2.0 5.0
4.5 5.0
Vin, Vout
tr, tf
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
AC Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
tr, tf ACT Devices except Schmitt Inputs
TJ Junction Temperature (PDIP)
TA Operating Ambient Temperature Range
IOH Output Current — HIGH
IOL Output Current — LOW
VCC @ 3.0 V
VCC @ 4.5 V
VCC @ 5.5 V
VCC @ 4.5 V
VCC @ 5.5 V
0
–40
150
40
25
10
8.0
25
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
Min
6.0
5.5
VCC
140
85
–24
24
Unit
V
V
ns/V
ns/V
°C
°C
mA
mA
FACT DATA
5-2





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