D-Type Flip-Flop. 74ACTQ374 Datasheet

74ACTQ374 Flip-Flop. Datasheet pdf. Equivalent

Part 74ACTQ374
Description Quiet Series Octal D-Type Flip-Flop
Feature 74ACQ374, 74ACTQ374 Quiet Series™ Octal D-Type Flip-Flop with 3-STATE Outputs April 2007 74ACQ374,.
Manufacture Fairchild Semiconductor
Datasheet
Download 74ACTQ374 Datasheet



74ACTQ374
April 2007
74ACQ374, 74ACTQ374
Quiet Series™ Octal D-Type Flip-Flop with 3-STATE
tm
Outputs
Features
ICC and IOZ reduced by 50%
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch-up immunity
Buffered positive edge-triggered clock
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24mA
Faster prop delays than the standard AC/ACT374
General Description
The ACQ/ACTQ374 is a high-speed, low-power octal
D-type flip-flop featuring separate D-type inputs for each
flip-flop and 3-STATE outputs for bus-oriented applica-
tions. A buffered Clock (CP) and Output Enable (OE) are
common to all flip-flops.
The ACQ/ACTQ374 utilizes FACT Quiet Series™ tech-
nology to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
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Ordering Information
Package
Order Number Number
Package Description
74ACQ374SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACQ374SJ
74ACTQ374SC
M20D
M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Body
74ACTQ374SJ
74ACTQ374QSC
M20D
MQA20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Description
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
www.fairchildsemi.com



74ACTQ374
Logic Symbol
IEEE/IEC
Logic Diagram
Functional Description
The ACQ/ACTQ374 consists of eight edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D-type inputs that meet the setup
and hold time requirements on the LOW-to-HIGH Clock
(CP) transition. With the Output Enable (OE) LOW, the
contents of the eight flip-flops are available at the out-
puts. When the OE is HIGH, the outputs go to the high
impedance state. Operation of the OE input does not
affect the state of the flip-flops.
Truth Table
Inputs
Dn CP OE
HL
LL
XXH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
Outputs
On
H
L
Z
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1989 Fairchild Semiconductor Corporation
74ACQ374, 74ACTQ374 Rev. 1.3
2
www.fairchildsemi.com





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