D-Type Flip-Flop. 74ACTQ574 Datasheet

74ACTQ574 Flip-Flop. Datasheet pdf. Equivalent

Part 74ACTQ574
Description Quiet Series Octal D-Type Flip-Flop
Feature 74ACQ574, 74ACTQ574 Quiet Series™ Octal D-Type Flip-Flop with 3-STATE Outputs April 2007 74ACQ574,.
Manufacture Fairchild Semiconductor
Datasheet
Download 74ACTQ574 Datasheet



74ACTQ574
April 2007
74ACQ574, 74ACTQ574
tm
Quiet Series™ Octal D-Type Flip-Flop with 3-STATE Outputs
Features
ICC and IOZ reduced by 50%
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
Functionally identical to the ACQ/ACTQ374
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24mA
Faster prop delays than the standard AC/ACT574
General Description
The ACQ/ACTQ574 is a high-speed, low-power octal
D-type flip-flop with a buffered Common Clock (CP) and
a buffered common Output Enable (OE). The information
presented to the D inputs is stored in the flip-flops on the
LOW-to-HIGH clock (CP) transition.
ACQ/ACTQ574 utilizes FACT Quiet Series™ technology
to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO™ output control and undershoot corrector in
addition to a split ground bus for superior performance.
The ACQ/ACTQ574 is functionally identical to the
ACTQ374 but with different pin-out.
Ordering Information
Order Number
74ACQ574SC
74ACQ574SJ
74ACTQ574SC
74ACTQ574SJ
Package
Number
M20B
M20D
M20B
M20D
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300"
Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CP
OE
O0–O7
Description
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
3-STATE Outputs
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1990 Fairchild Semiconductor Corporation
74ACQ574, 74ACTQ574 Rev. 1.3
www.fairchildsemi.com



74ACTQ574
Logic Symbols
IEEE/IEC
Logic Diagram
Functional Description
The ACQ/ACTQ574 consists of eight edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The buffered clock and buffered Output Enable
are common to all flip-flops. The eight flip-flops will store
the state of their individual D-type inputs that meet the
setup and hold time requirements on the LOW-to-HIGH
Clock (CP) transition. With the Output Enable (OE)
LOW, the contents of the eight flip-flops are available at
the outputs. When OE is HIGH, the outputs go to the
high impedance state. Operation of the OE input does
not affect the state of the flip-flops.
Function Table
Inputs
OE CP D
HH L
HHH
HL
HH
LL
LH
LHL
L HH
Internal
Q
NC
NC
L
H
L
H
NC
NC
Outputs
ON Function
Z Hold
Z Hold
Z Load
Z Load
L Data Available
H Data Available
NC No Change in
Data
NC No Change in
Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
©1990 Fairchild Semiconductor Corporation
74ACQ574, 74ACTQ574 Rev. 1.3
2
www.fairchildsemi.com





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