Display Controller. MM74C991 Datasheet

MM74C991 Controller. Datasheet pdf. Equivalent

Part MM74C991
Description 4-Digit Expandable Segment Display Controller
Feature MM74C911 4-Digit Expandable Segment Display Controller October 1987 Revised January 1999 MM74C911 .
Manufacture Fairchild Semiconductor
Download MM74C991 Datasheet

October 1987
Revised January 1999
4-Digit Expandable Segment Display Controller
General Description
The MM74C911 display controller is an interface element
with memory that drives a 4-digit, 8-segment LED display.
The MM74C911 allows individual control of any segment in
the 4-digit display. The number of segments per digit can
be expanded without any external components. For exam-
ple, two MM74C911’s can be cascaded to drive a 16-seg-
ment alpha-numeric display.
The display controllers receive data information through 8
data lines a, b…DP, and digit information through 2
address inputs K1 and K2. The input data is written into the
register selected by the address information when CHIP
ENABLE, CE, and WRITE ENABLE, WE, are LOW and is
latched when either CE or WE return HIGH. Data hold time
is not required.
A self-contained internal oscillator sequentially presents
the stored data to high drive (100 mA typ.) 3-STATE output
drivers which directly drive the LED display. The drivers are
active when the control pin labeled SEGMENT OUTPUT
ENABLE, SOE, is LOW and go into 3-STATE when SOE is
HIGH. This feature allows for duty cycle brightness control,
or for disabling the output drive for power conservation.
The digit outputs directly drive the base of the digit transis-
tor when the control pin labeled DIGIT INPUT OUTPUT,
DIO, is LOW. When DIO is HIGH, the digit lines turn into
inputs and the internal scanning multiplexer is disabled.
When any digit line is forced HIGH by an external device,
usually another MM74C911, the data information for that
digit is presented to the output. In this manner, 16-segment
alpha-numeric displays, 24- or 32-segment displays, or an
array of discrete LED's can be controlled by the simple cas-
cading of expandable segment display controllers. All
inputs except digit inputs are TTL compatible and do not
clamp input voltages above VCC.
s Direct segment drive (100 mA typ.) 3-STATE
s 4 registers addressed like RAM
s Internal oscillator and scanning circuit
s Direct base drive to digit transistor
s Segment expandability without external components
s TTL compatible inputs
s Power saver mode—5 µW (typ.)
Ordering Code:
Order Number Package Number
Package Description
28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS010, 0.600” Wide
Connection Diagram
Pin Assignments for DIP
Top View
© 1999 Fairchild Semiconductor Corporation DS005915.prf

Truth Tables
Input Control
CE Address WE
K2 K1
0 0 0 0 Write Digit 1
0 0 0 1 Latch Digit 1
0 0 1 0 Write Digit 2
0 0 1 1 Latch Digit 2
0 1 0 0 Write Digit 3
0 1 0 1 Latch Digit 3
0 1 1 0 Write Digit 4
0 1 1 1 Latch Digit 4
1 X X X Disable Writing
Output Control
DIO SOE Digit Lines
D4 D3 D2 D1
0 0 R R R R Refresh Display
0 1 R R R R Disable Segment Outputs
1 0 0 0 0 0 Digits Are Now Inputs
1 0 0 0 0 1 Display Digit 1
1 0 0 0 1 0 Display Digit 2
1 0 0 1 0 0 Display Digit 3
1 0 1 0 0 0 Display Digit 4
1 1 0 0 0 0 Power Saver Mode
R = Refresh (digit lines sequentially pulsed)
X = Don’t Care
Functional Description
The MM74C911 display controller is manufactured on stan-
dard metal gate CMOS technology. A single 5V 74 series
TTL supply can be used for power and should be bypassed
at the VCC pin to suppress current transients.
The digit outputs directly drive the base of a grounded
emitter digit transistor without the need of a Darlington con-
figuration. If an MM74C911 is driving a digit transistor and
also supplying digit information to a cascaded MM74C911,
base resistors are needed in the digit transistors to provide
an adequate high level to the digit inputs of the cascaded
As seen in the Block Diagram, these display controllers
contain four 8-bit registers; any one may be randomly writ-
ten into. In normal operation, the internal multiplexer scans
the registers and refreshes the display. In cascaded opera-
tion, 1 MM74C911 serves as a master refresh device and
cascaded MM74C911’s are slaved to it through digit lines
operating as inputs.
The MM74C911 appears to a microprocessor as memory
and to the user as a self-scan display. Since every seg-
ment is under microprocessor control, great versatility is
Low power standby operation occurs with both SOE and
DIO inputs HIGH. This condition forces the MM74C911 to a
quiescent state typically drawing less than 1 µA of supply
current with a standby supply voltage as low as 3V.
Logic Diagram

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