Edge-Triggered Flip-Flop. 74F109 Datasheet

74F109 Flip-Flop. Datasheet pdf. Equivalent

Part 74F109
Description Dual JK Positive Edge-Triggered Flip-Flop
Feature 54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK P.
Manufacture National Semiconductor
Datasheet
Download 74F109 Datasheet



74F109
November 1994
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ’F74
data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
n Guaranteed 4000V minimum ESD protection.
Ordering Code: See Section 0
Commercial
Military
74F109PC
74F109SC (Note 1)
54F109DM (Note 2)
74F109SJ (Note 1)
54F109FM (Note 2)
54F109LM (Note 2)
Package
Number
N16E
J16A
M16A
M16D
W16A
E20A
Package Description
16-Lead (0.300" Wide) Molded Dual-in-Line
16-Lead Ceramic Dual-in-Line
16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
16-Lead Cerpack
16-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
DSXXX
DS009471-3
DS009471-4
DS009471-6
FAST® and TRI-STATE® are registered trademarks of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation DS009471
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv Proof
www.national.com
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74F109
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
DS009471-1
DS009471-2
Unit Loading/Fan Out
See Section 0 for U.L. definitions
Pin Names
Description
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs (Active Rising Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
54F/74F
U.L.
HIGH/LOW
1.0/1.0
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
1.0/1.0
20 µA/−0.6 mA
1.0/3.0
20 µA/−1.8 mA
1.0/3.0
20 µA/−1.8 mA
50/33.3
−1 mA/20 mA
Truth Table
Inputs
Outputs
SD CD CP J K
L H X XX
Q
H
Q
L
H L X XX L H
L L X XX H H
H HNl l L H
H H Nh l
Toggle
H H N l h Q0 Q0
H H Nhh H L
H H L X X Q0 Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
N = LOW-to-HIGH Transition
X = Immaterial
Q0 (Q0) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
DSXXX
www.national.com
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PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof
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