Binary Counter. 74F163A Datasheet

74F163A Counter. Datasheet pdf. Equivalent

Part 74F163A
Description Synchronous Presettable Binary Counter
Feature 74F161A • 74F163A Synchronous Presettable Binary Counter April 1988 Revised July 1999 74F161A • 74.
Manufacture Fairchild Semiconductor
Datasheet
Download 74F163A Datasheet



74F163A
April 1988
Revised July 1999
74F161A • 74F163A
Synchronous Presettable Binary Counter
General Description
The 74F161A and 74F163A are high-speed synchronous
modulo-16 binary counters. They are synchronously pre-
settable for application in programmable dividers and have
two types of Count Enable inputs plus a Terminal Count
output for versatility in forming synchronous multi-stage
counters. The 74F161A has an asynchronous Master-
Reset input that overrides all other inputs and forces the
outputs LOW. The 74F163A has a Synchronous Reset
input that overrides counting and parallel loading and
allows the outputs to be simultaneously reset on the rising
edge of the clock. The 74F161A and 74F163A are high-
speed versions of the 74F161 and 74F163.
Features
s Synchronous counting and loading
s High-speed synchronous expansion
s Typical count frequency of 120 MHz
Ordering Code:
Order Number Package Number
Package Description
74F161ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F161ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F161APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74F163ASC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F163ASJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F163APC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74F161A
74F163A
© 1999 Fairchild Semiconductor Corporation DS009486
www.fairchildsemi.com



74F163A
Logic Symbols
74F161A
IEEE/IEC
74F163A
IEEE/IEC
74F161A
74F163A
Unit Loading/Fan Out
Pin Names
Description
CEP
Count Enable Parallel Input
CET
Count Enable Trickle Input
CP Clock Pulse Input (Active Rising Edge)
MR (74F161A) Asynchronous Master Reset Input (Active LOW)
SR (74F163A) Synchronous Reset Input (Active LOW)
P0–P3
PE
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Q0–Q3
TC
Flip-Flop Outputs
Terminal Count Output
U.L.
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/0.6 mA
20 µA/1.2 mA
20 µA/0.6 mA
20 µA/0.6 mA
20 µA/1.2 mA
20 µA/0.6 mA
20 µA/1.2 mA
1 mA/20 mA
1 mA/20 mA
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