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IDT54FCT16H501ET Dataheets PDF



Part Number IDT54FCT16H501ET
Manufacturers IDT
Logo IDT
Description FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Datasheet IDT54FCT16H501ET DatasheetIDT54FCT16H501ET Datasheet (PDF)

Integrated Device Technology, Inc. FAST CMOS 18-BIT REGISTERED TRANSCEIVER IDT54/74FCT16501AT/CT/ET IDT54/74FCT162501AT/CT/ET IDT54/74FCT162H501AT/CT/ET FEATURES: CMOS technology. These high-speed, low-power 18-bit reg- • Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in transparent, latched and clocked – High-speed, low-power CMOS replacement for ABT functions modes. Data flow in each direction is .

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Integrated Device Technology, Inc. FAST CMOS 18-BIT REGISTERED TRANSCEIVER IDT54/74FCT16501AT/CT/ET IDT54/74FCT162501AT/CT/ET IDT54/74FCT162H501AT/CT/ET FEATURES: CMOS technology. These high-speed, low-power 18-bit reg- • Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in transparent, latched and clocked – High-speed, low-power CMOS replacement for ABT functions modes. Data flow in each direction is controlled by output- enable (OEAB and OEBA), latch enable (LEAB and LEBA) – Typical tSK(o) (Output Skew) < 250ps and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, – Low input and output leakage ≤ 1µA (max.) the device operates in transparent mode when LEAB is HIGH. – ESD > 2000V per MIL-STD-883, Method 3015; When LEAB is LOW, the A data is latched if CLKAB is held at > 200V using machine model (C = 200pF, R = 0) a HIGH or LOW logic level. If LEAB is LOW, the A bus.


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