MT48LC16M8A2

SDR SDRAM MT48LC32M4A2 – 8 Meg x 4 x 4 Banks MT48LC16M8A2 – 4 Meg x 8 x 4 Banks MT48LC8M16A2 – 2 Meg x 16 x 4 Banks 128Mb: x4, x8, x16 SDRAM Features Features PC100- and PC133-compliant Fully synchronous; all signals registered on positive edge of system clock Internal, pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths (BL): 1, 2, 4, 8, or full page Auto precharge, includes concurrent auto precharge and auto refresh modes Self refresh modes: Standard and low power (not available on AT devices) Auto Refresh – 64ms, 4096-cycle refresh (commercial and industrial) – 16ms, 4096-cycle refresh (automotive) LVTTL-compatible inputs and outputs Single 3.3V ±0.3V power supply Options Configurations – 32 Meg x 4 (8 Meg x 4 x 4 banks)1 – 16 Meg x 8 (4 Meg x 8 x 4 banks) – 8 Meg x 16 (2 Meg x 16 x 4 banks) Write recovery (tWR) – tWR = 2 C...