LPDDR2 SDRAM. EDB2432B4 Datasheet

EDB2432B4 SDRAM. Datasheet pdf. Equivalent

Part EDB2432B4
Description Embedded LPDDR2 SDRAM
Feature Embedded LPDDR2 SDRAM Features Embedded LPDDR2 SDRAM EDB1316BD, EDB1332BD, EDB2432B4, EDB4064B4 Fe.
Manufacture Micron
Datasheet
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EDB2432B4
Embedded LPDDR2 SDRAM
Features
Embedded LPDDR2 SDRAM
EDB1316BD, EDB1332BD, EDB2432B4, EDB4064B4
Features
• Ultra low-voltage core and I/O power supplies
– VDD2 = 1.14–1.30V
– VDDCA/VDDQ = 1.14–1.30V
– VDD1 = 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed
Grade
1D
Clock Rate Data Rate
(MHz)
(Mb/s/pin) RL WL
533
1066
84
Options
• Density/Page Size
– 1Gb/2KB - single die
– 2Gb/2KB - dual die
– 4Gb/2KB - quad die
• Organization
– x16
– x32
– x64
• VDD2: 1.2V
• Revision
– Single die
– Multi-die
• FBGA “green” package
– 134-ball FBGA
– 134-ball multi-die FBGA
– 168-ball FBGA
for PoP
– 216-ball multi-die FBGA
for PoP
• Timing – cycle time
– 1.875ns @ RL = 8
• Operating temperature range
– From –30°C to +85°C
– From –40°C to +85°C
Marking
13
24
40
16
32
64
B
D
4
BH
MA
PC
PB
-1D
(Blank)
IT
Table 2: S4 Configuration Addressing
Architecture
Die configura-
tion
Row addressing
Column ad-
dressing
Number of die
Die per rank
Ranks per chan-
nel1
64 Meg x 16
8 Meg x 16 x 8 banks
8K (A[12:0])
1K (A[9:0])
1
1
1
32 Meg x 32
4 Meg x 32 x 8 banks
64 Meg x 32
64 Meg x 64
2 x 8 Meg x 16 x 8 banks 4 x 8 Meg x 16 x 8 banks
8K (A[12:0])
512 (A[8:0])
8K (A[12:0])
1K (A[9:0])
8K (A[12:0])
1K (A[9:0])
124
122
112
Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins.
X26P4QTWDSPK-13-10152
u98m_lpddr2_embedded.pdf - Rev. E 11/16 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.



EDB2432B4
Embedded LPDDR2 SDRAM
Features
Figure 1: LPDDR2 Part Numbering
E D B 13 32 B D BH -1D IT -F
Embedded Memory
Type
D = Packaged device
Product Family
B = DDR2 Mobile RAM
Density
13 = 1Gb/2KB
24 = 2Gb/2KB
40 = 4Gb/2KB
Organization
16 = x16
32 = x32
64 = x64
Power Supply and Interface
B = VDD1 = 1.8V; VDD2 = VDDQ = 1.2V;
S4B device; HSUL
Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free
Operating Temperature
IT = –40°C to +85°C
Blank = –30°C to +85°C
Speed (package only)
1D = 1066 Mbps
Package
BH = 134-ball VFBGA (10mm x 11.5mm)
MA = 134-ball VFBGA (10mm x 11.5mm)
PC = 168-ball WFBGA (12mm x 12mm)
PB = 216-ball WFBGA (12mm x 12mm)
Revision
D (for single-die)
4 (for multi-die)
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
Table 3: Package Codes and Descriptions
Package
Code
BH
MA
PC
PB
Ball Count
134
134
168
216
# Ranks
1
1
1
2
# Channels Size (mm)
1 10 x 11.5 x 1.0, 0.65 pitch
1 10 x 11.5 x 1.0, 0.65 pitch
1 12 x 12 x 0.8, 0.5 pitch
2 12 x 12 x 0.8, 0.4 pitch
Die per
Package
SDP
DDP
SDP
QDP
Notes: 1. SDP = single-die package; DDP = Dual-die package; QDP = Quad-die package;.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
Solder Ball
Composition
SAC302
SAC302
SAC302
SAC302
X26P4QTWDSPK-13-10152
u98m_lpddr2_embedded.pdf - Rev. E 11/16 EN
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.





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