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MT49H16M18 Dataheets PDF



Part Number MT49H16M18
Manufacturers Micron Technology
Logo Micron Technology
Description 16 Meg x 18 x 8 Banks CIO RLDRAM 2
Datasheet MT49H16M18 DatasheetMT49H16M18 Datasheet (PDF)

CIO RLDRAM 2 MT49H32M9 – 32 Meg x 9 x 8 Banks MT49H16M18 – 16 Meg x 18 x 8 Banks MT49H8M36 – 8 Meg x 36 x 8 Banks 288Mb: x9, x18, x36 CIO RLDRAM 2 Features Features • 533 MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36 • 8 internal banks for concurrent operation and maxi- mum bandwidth • Reduced cycle time (15ns at 533 MHz) • Nonmultiplexed addresses (address multiplexing option av.

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CIO RLDRAM 2 MT49H32M9 – 32 Meg x 9 x 8 Banks MT49H16M18 – 16 Meg x 18 x 8 Banks MT49H8M36 – 8 Meg x 36 x 8 Banks 288Mb: x9, x18, x36 CIO RLDRAM 2 Features Features • 533 MHz DDR operation (1.067 Gb/s/pin data rate) • 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency) • Organization – 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36 • 8 internal banks for concurrent operation and maxi- mum bandwidth • Reduced cycle time (15ns at 533 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask for WRITE commands • Differential input clocks (CK, CK#) • Differential input data clocks (DKx, DKx#) • On-die DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (8K refresh for each bank; 64K refresh command .


MT49H32M9 MT49H16M18 MT49H8M36


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