288Mb: x9, x18, x36 CIO RLDRAM 2
Ball Assignments and Descriptions
Table 4: Ball Descriptions
Address inputs: A0–A20 define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings. They are sampled
at the rising edge of CK.
BA0–BA2 Input Bank address inputs: Select to which internal bank a command is being applied.
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS# Input Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
Input data clock: DK and DK# are the differential input data clocks. All input data is referenced
to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0–
DQ17 are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For
the x9 and x18 devices, all DQs are referenced to DK and DK#. All DKx and DKx# pins must al-
ways be supplied to the device.
DM Input Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked
when DM is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration).
Tie signal to ground if not used.
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with
CS#) the command to be executed.
DQ0–DQ35 I/O Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is refer-
enced to both edges of QKx. During WRITE commands, the data is sampled at both edges of DK.
ZQ Reference External impedance (25–60Ω): This signal is used to tune the device outputs to the system da-
ta bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal
to ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to
VDD invokes the maximum impedance mode. Refer to the Mode Register Definition in Nonmulti-
plexed Address Mode figure to activate this function.
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free-run-
ning, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is ideally
180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with DQ0–
DQ17, and QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0# are
aligned with DQ0–DQ8, while QK1 and QK1# are aligned with Q9–Q17. For the x9 device, all DQs
are aligned with QK0 and QK0#.
Output Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and
Output IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
VDD Supply Power supply: Nominally, 1.8V. See the DC Electrical Characteristics and Operating Conditions
table for range.
Supply DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
See the DC Electrical Characteristics and Operating Conditions table for range.
Supply Power supply: Nominally, 2.5V. See the DC Electrical Characteristics and Operating Conditions
table for range.
rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN
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