288Mb: x9, x18, x36 CIO RLDRAM 2
The Micron® reduced latency DRAM (RLDRAM®) 2 is a high-speed memory device de-
signed for high-bandwidth data storage such as telecommunications, networking, and
cache applications. The chip’s 8-bank architecture is optimized for sustainable high-
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output
data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative
edges of the input data clock(s).
Read and write accesses to the device are burst-oriented. The burst length (BL) is pro-
grammable to 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
Bank-scheduled refresh is supported with the row address generated internally.
The 144-ball package is used to enable ultra high-speed data transfer rates and a simple
upgrade path from early generation devices.
Figure 2: State Diagram
rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN
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