Dual J-K Flip-Flops (with Preset and Clear)
Oct 11, 2005
Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to
the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of
the clock and accomplished by a low logic level on the corresponding input.
• High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
• Ordering Information
HD74HC112FPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
L HXX XH L
L L X X X H*1 H*1
HH L X X
H : High level
L : Low level
X : Irrelevant
Note: 1. Q and Q will remain High as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and
Clear go High simultaneously.
Rev.2.00, Oct 11, 2005 page 1 of 6