4-bit D-type Register (with 3-state outputs)
Jan 31, 2006
The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be
used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in
the logic high level.
The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of
the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Clearing is enabled by taking the clear input to a logic high level. The data outputs change
state on the positive going edge of the clock.
• High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC173FPEL SOP-16 pin (JEITA)
HD74HC173RPEL SOP-16 pin (JEDEC)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
L L X X X Q0
L H X X Q0
L X H X Q0
L L LHH
Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however sequential
operation of the flip-flops is not affected.
QAo to QHo = Outputs remain unchanged.
QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input.
H : High level
L : Low level
X : Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 7