Programmable Frequency Divider/Digital Timer
Jan 31, 2006
This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs.
It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which
initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate
Test Point output is provided with HD74HC294 to facilitate incoming inspections.
• High Speed Operation: tpd (Clock to Q) = 16 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
HD74HC294FPEL SOP-16 pin (JEITA)
Note: Please consult the sales office for the above package availability.
EL (2,000 pcs/reel)
H : high level
L : low level
Q Output Mode
Cleared to L
Rev.2.00 Jan 31, 2006 page 1 of 9