HD74LS195A

HD74LS195A 4-bit Parallel-Access Shift Register REJ03D0457–0300 Rev.3.00 Jul.15.2005 This 4-bit register features parallel inputs, parallel outputs, J-K serial inputs, shift / load control input, and a direct overriding clear. All inputs are buffered to lower the input drive requirements. The registers have two modes of operation: Parallel (broadside) load Shift (in the direction QA toward QD) Parallel loading is accomplished by applying the four bits of data and taking the shift / load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shifting is accomplished synchronously when the shift / load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D-, or Ttype flip-flop as shown in the function table. Features Ordering Information Part Name Pack...