Document
HD74LS257
Quadruple 2-line-to-1-line Data Selectors / Multiplexers (with not inverted 3-state outputs)
REJ03D0469–0300 Rev.3.00
Jul.15.2005
This multiplexer features three-state outputs that can interface directly with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (at a high-impedance state) the low impedance of the single enabled output will drive the bus line to a high or low logic level.
To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the outputenable circuitry is designed such that the output disable times are shorter than the output enable times.
Features
• Ordering Information
Part Name
Package Type
Package Code (Previous Code)
Package Abbreviation
HD74LS257P
DILP-16 pin
PRDP0016AE-B (DP-16FV)
P
HD74LS257FPEL SOP-16 pin (JEITA)
PRSP0016DH-B (FP-16DAV)
FP
Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantit.