HD74LS293

HD74LS293 4-bit Binary Counter REJ03D0477–0300 Rev.3.00 Jul.15.2005 This counter contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and divideby-eight counter. This counter has a gated zero reset. To use the maximum count length of this counter, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate function table. Features Ordering Information Part Name HD74LS293P Package Type DILP-14 pin Package Code (Previous Code) PRDP0014AB-B (DP-14AV) Package Abbreviation P Taping Abbreviation (Quantity) — Pin Arrangement NC 1 NC 2 NC 3 QC Outputs QB 4 5 NC 6 GND 7 R0(2) R0(1) QC B QB A QA QD (Top view) 14 VCC 13 R0(2) 12 R0(1) 11 B 10 A Inputs 9 QA Outputs 8 QD Function Table Reset / Count Reset Input R0 (1) R0 (2) HH LX XL QD L Outputs QC QB LL Count Count QA L Rev.3.00, Jul.15.2005, page 1 of 7 HD74LS293 BCD Count Sequenc...